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/linux-6.14.4/arch/arm64/boot/dts/renesas/
Dsalvator-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for common parts of Salvator-X board variants
5 * Copyright (C) 2015-2016 Renesas Electronics Corp.
9 * SSI-AK4613
13 * amixer set "DVC Out" 100%
18 * amixer set "DVC Out Mute" on
23 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
24 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
25 * amixer set "DVC Out Ramp" on
27 * amixer set "DVC Out" 80% // Volume Down
[all …]
Dulcb.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car Gen3 ULCB board
10 * > amixer set "DVC Out" 1%
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
18 model = "Renesas R-Car Gen3 ULCB board";
37 stdout-path = "serial0:115200n8";
40 audio_clkout: audio-clkout {
43 * but needed to avoid cs2000/rcar_sound probe dead-lock
45 compatible = "fixed-clock";
[all …]
/linux-6.14.4/Documentation/driver-api/media/
Dcamera-sensor.rst1 .. SPDX-License-Identifier: GPL-2.0
8 This document covers the in-kernel APIs only. For the best practices on
12 CSI-2, parallel and BT.656 buses
13 --------------------------------
15 Please see :ref:`transmitter-receiver`.
18 ---------------
20 Camera sensors have an internal clock tree including a PLL and a number of
21 divisors. The clock tree is generally configured by the driver based on a few
22 input parameters that are specific to the hardware: the external clock frequency
23 and the link frequency. The two parameters generally are obtained from system
[all …]
/linux-6.14.4/arch/powerpc/boot/dts/
Dkmeter1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * 2008-2011 DENX Software Engineering GmbH
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
36 d-cache-size = <32768>; // L1, 32K
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <[email protected]>
11 - Florian Fainelli <[email protected]>
12 - Heiner Kallweit <[email protected]>
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
22 description: Clock output frequency in Hertz.
26 qca,clk-out-strength:
[all …]
Dti,dp83822.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <[email protected]>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
24 - $ref: ethernet-phy.yaml#
30 ti,link-loss-low:
39 ti,fiber-mode:
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dsilabs,si5341.txt2 i2c clock generator.
6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
12 The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
15 The internal structure of the clock generators can be found in [2].
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
33 - compatible: shall be one of the following:
34 "silabs,si5340" - Si5340 A/B/C/D
35 "silabs,si5341" - Si5341 A/B/C/D
[all …]
/linux-6.14.4/drivers/gpu/drm/i915/gt/
Dintel_gt_clock_utils.c1 // SPDX-License-Identifier: MIT
63 * Note that on gen11+, the clock frequency may be reconfigured. in gen11_read_clock_frequency()
66 * First figure out the reference frequency. There are 2 ways in gen11_read_clock_frequency()
67 * we can compute the frequency, either through the in gen11_read_clock_frequency()
79 * Now figure out how the command stream's timestamp in gen11_read_clock_frequency()
80 * register increments from this frequency (it might in gen11_read_clock_frequency()
81 * increment only every few clock cycle). in gen11_read_clock_frequency()
83 freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> in gen11_read_clock_frequency()
98 freq = IS_GEN9_LP(uncore->i915) ? 19200000 : 24000000; in gen9_read_clock_frequency()
101 * Now figure out how the command stream's timestamp in gen9_read_clock_frequency()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/can/
Dcc770.txt8 - compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
11 - reg : should specify the chip select, address offset and size required
14 - interrupts : property with a value describing the interrupt source
19 - bosch,external-clock-frequency : frequency of the external oscillator
20 clock in Hz. Note that the internal clock frequency used by the
24 - bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin.
28 - bosch,slew-rate : slew rate of the CLKOUT signal. If not specified,
31 - bosch,disconnect-rx0-input : see data sheet.
33 - bosch,disconnect-rx1-input : see data sheet.
35 - bosch,disconnect-tx1-output : see data sheet.
[all …]
Dnxp,sja1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <[email protected]>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - enum:
20 - renesas,r9a06g032-sja1000 # RZ/N1D
[all …]
/linux-6.14.4/arch/arm/boot/dts/renesas/
Dr8a7791-koelsch.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2013-2014 Renesas Solutions Corp.
11 * SSI-AK4643
20 * amixer set "DVC Out" 100%
25 * amixer set "DVC Out Mute" on
30 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
31 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
32 * amixer set "DVC Out Ramp" on
34 * amixer set "DVC Out" 80% // Volume Down
35 * amixer set "DVC Out" 100% // Volume Up
[all …]
Dr8a7790-lager.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
7 * Copyright (C) 2015-2016 Renesas Electronics Corporation
11 * SSI-AK4643
20 * amixer set "DVC Out" 100%
25 * amixer set "DVC Out Mute" on
30 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
31 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
32 * amixer set "DVC Out Ramp" on
34 * amixer set "DVC Out" 80% // Volume Down
[all …]
Dr8a7793-gose.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2015 Renesas Electronics Corporation
9 * SSI-AK4643
18 * amixer set "DVC Out" 100%
23 * amixer set "DVC Out Mute" on
28 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
29 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
30 * amixer set "DVC Out Ramp" on
32 * amixer set "DVC Out" 80% // Volume Down
33 * amixer set "DVC Out" 100% // Volume Up
[all …]
/linux-6.14.4/drivers/clk/analogbits/
Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
13 * The bulk of this code is primarily useful for clock configurations
14 * that must operate at arbitrary rates, as opposed to clock configurations
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
33 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
35 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/iio/frequency/
Dadi,adrf6780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/frequency/adi,adrf6780.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <[email protected]>
14 radio designs operating in the 5.9 GHz to 23.6 GHz frequency range.
21 - adi,adrf6780
26 spi-max-frequency:
31 Definition of the external clock.
34 clock-names:
[all …]
/linux-6.14.4/Documentation/timers/
Dtimekeeping.rst2 Clock sources, Clock events, sched_clock() and delay timers
7 drivers/clocksource in the kernel tree, but the code may be spread out
10 If you grep through the kernel source you will find a number of architecture-
11 specific implementations of clock sources, clockevents and several likewise
12 architecture-specific overrides of the sched_clock() function and some
15 To provide timekeeping for your platform, the clock source provides
16 the basic timeline, whereas clock events shoot interrupts on certain points
17 on this timeline, providing facilities such as high-resolution timers.
22 Clock sources
23 -------------
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/sound/
Dsimple-card.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <[email protected]>
14 frame-master:
15 description: Indicates dai-link frame master.
18 bitclock-master:
19 description: Indicates dai-link bit clock master
22 frame-inversion:
[all …]
/linux-6.14.4/sound/aoa/soundbus/i2sbus/
Dinterface.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * i2sbus driver -- interface register definitions
61 * - clock source
62 * - MClk divisor
63 * - SClk divisor
64 * - SClk master flag
65 * - serial format (sony, i2s 64x, i2s 32x, dav, silabs)
66 * - external sample frequency interrupt (don't understand)
67 * - external sample frequency
70 /* clock source. You get either 18.432, 45.1584 or 49.1520 MHz */
[all …]
/linux-6.14.4/drivers/cpufreq/
Dpasemi-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
48 /* We support 5(A0-A4) power states excluding turbo(A5-A6) modes */
132 int err = -ENODEV; in pas_cpufreq_cpu_init()
134 cpu = of_get_cpu_node(policy->cpu, NULL); in pas_cpufreq_cpu_init()
136 goto out; in pas_cpufreq_cpu_init()
138 max_freqp = of_get_property(cpu, "clock-frequency", NULL); in pas_cpufreq_cpu_init()
141 err = -EINVAL; in pas_cpufreq_cpu_init()
142 goto out; in pas_cpufreq_cpu_init()
148 dn = of_find_compatible_node(NULL, NULL, "1682m-sdc"); in pas_cpufreq_cpu_init()
151 "pasemi,pwrficient-sdc"); in pas_cpufreq_cpu_init()
[all …]
/linux-6.14.4/Documentation/virt/hyperv/
Dclocks.rst1 .. SPDX-License-Identifier: GPL-2.0
7 -----
8 On arm64, Hyper-V virtualizes the ARMv8 architectural system counter
12 architectural system counter is functional in guest VMs on Hyper-V.
13 While Hyper-V also provides a synthetic system clock and four synthetic
14 per-CPU timers as described in the TLFS, they are not used by the
15 Linux kernel in a Hyper-V guest on arm64. However, older versions
16 of Hyper-V for arm64 only partially virtualize the ARMv8
19 Linux kernel versions on these older Hyper-V versions requires an
20 out-of-tree patch to use the Hyper-V synthetic clocks/timers instead.
[all …]
/linux-6.14.4/drivers/crypto/intel/qat/qat_common/
Dadf_clock.c1 // SPDX-License-Identifier: GPL-2.0-only
41 static int measure_clock(struct adf_accel_dev *accel_dev, u32 *frequency) in measure_clock() argument
58 delta_us = timespec_to_us(&ts2) - timespec_to_us(&ts1); in measure_clock()
59 } while (delta_us > MEASURE_CLOCK_DELTA_THRESHOLD_US && --tries); in measure_clock()
62 dev_err(&GET_DEV(accel_dev), "Excessive clock measure delay\n"); in measure_clock()
63 return -ETIMEDOUT; in measure_clock()
74 return -EIO; in measure_clock()
77 delta_us = timespec_to_us(&ts4) - timespec_to_us(&ts3); in measure_clock()
78 } while (delta_us > MEASURE_CLOCK_DELTA_THRESHOLD_US && --tries); in measure_clock()
81 dev_err(&GET_DEV(accel_dev), "Excessive clock measure delay\n"); in measure_clock()
[all …]
/linux-6.14.4/arch/arm64/boot/dts/amlogic/
Dmeson-g12a-sei510.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-g12a.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/meson-g12a-gpio.h>
12 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
19 compatible = "adc-keys";
20 io-channels = <&saradc 0>;
21 io-channel-names = "buttons";
[all …]
Dmeson-g12a-x96-max.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-g12a.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-g12a-gpio.h>
11 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
14 compatible = "amediatech,x96-max", "amlogic,g12a";
22 spdif_dit: audio-codec-1 {
23 #sound-dai-cells = <0>;
24 compatible = "linux,spdif-dit";
[all …]
/linux-6.14.4/arch/arm/boot/dts/ti/omap/
Ddra7-evm-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
6 #include "dra74-ipu-dsp-common.dtsi"
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/ti-dra7-atl.h>
9 #include <dt-bindings/input/input.h>
13 stdout-path = &uart1;
17 compatible = "linux,extcon-usb-gpio";
18 id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
22 compatible = "linux,extcon-usb-gpio";
[all …]
/linux-6.14.4/drivers/i2c/busses/
Di2c-synquacer.c1 // SPDX-License-Identifier: GPL-2.0
28 #define SYNQUACER_I2C_REG_CCR (0x02 << 2) // Clock Control
32 #define SYNQUACER_I2C_REG_FSR (0x06 << 2) // Bus Clock Freq
54 #define SYNQUACER_I2C_CCR_CS_MASK (0x1f) // CCR Clock Period Sel.
58 #define SYNQUACER_I2C_CSR_CS_MASK (0x3f) // CSR Clock Period Sel.
65 /* PCLK frequency */
68 /* STANDARD MODE frequency */
70 DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_MAX_STANDARD_MODE_FREQ) - 2, 2)
71 /* FAST MODE frequency */
73 DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_MAX_FAST_MODE_FREQ) - 2) * 2, 3)
[all …]

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