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/linux-6.14.4/drivers/phy/qualcomm/
Dphy-qcom-qmp.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include "phy-qcom-qmp-qserdes-com.h"
10 #include "phy-qcom-qmp-qserdes-txrx.h"
12 #include "phy-qcom-qmp-qserdes-com-v3.h"
13 #include "phy-qcom-qmp-qserdes-txrx-v3.h"
15 #include "phy-qcom-qmp-qserdes-com-v4.h"
16 #include "phy-qcom-qmp-qserdes-txrx-v4.h"
17 #include "phy-qcom-qmp-qserdes-txrx-v4_20.h"
19 #include "phy-qcom-qmp-qserdes-com-v5.h"
20 #include "phy-qcom-qmp-qserdes-txrx-v5.h"
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Dphy-qcom-qmp-usbc.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
17 #include <linux/phy/phy.h>
26 #include "phy-qcom-qmp-common.h"
28 #include "phy-qcom-qmp.h"
29 #include "phy-qcom-qmp-pcs-misc-v3.h"
33 /* set of registers with offsets different per-PHY */
35 /* PCS registers */
289 u16 pcs; member
298 /* struct qmp_phy_cfg - per-PHY initialization config */
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Dphy-qcom-qmp-ufs.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
16 #include <linux/phy/phy.h>
24 #include "phy-qcom-qmp-common.h"
26 #include "phy-qcom-qmp.h"
27 #include "phy-qcom-qmp-pcs-ufs-v2.h"
28 #include "phy-qcom-qmp-pcs-ufs-v3.h"
29 #include "phy-qcom-qmp-pcs-ufs-v4.h"
30 #include "phy-qcom-qmp-pcs-ufs-v5.h"
31 #include "phy-qcom-qmp-pcs-ufs-v6.h"
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Dphy-qcom-qmp-pcie-msm8996.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
16 #include <linux/phy/phy.h>
22 #include "phy-qcom-qmp-common.h"
24 #include "phy-qcom-qmp.h"
36 /* set of registers with offsets different per-PHY */
43 /* PCS registers */
139 /* struct qmp_phy_cfg - per-PHY initialization config */
144 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
169 * struct qmp_phy - per-lane phy descriptor
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Dphy-qcom-qmp-usb-legacy.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
17 #include <linux/phy/phy.h>
23 #include "phy-qcom-qmp.h"
24 #include "phy-qcom-qmp-pcs-misc-v3.h"
25 #include "phy-qcom-qmp-pcs-usb-v4.h"
26 #include "phy-qcom-qmp-pcs-usb-v5.h"
28 #include "phy-qcom-qmp-dp-com-v3.h"
31 /* DP PHY soft reset */
33 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
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Dphy-qcom-qmp-usb.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
16 #include <linux/phy/phy.h>
22 #include "phy-qcom-qmp-common.h"
24 #include "phy-qcom-qmp.h"
25 #include "phy-qcom-qmp-pcs-misc-v3.h"
26 #include "phy-qcom-qmp-pcs-misc-v4.h"
27 #include "phy-qcom-qmp-pcs-usb-v4.h"
28 #include "phy-qcom-qmp-pcs-usb-v5.h"
29 #include "phy-qcom-qmp-pcs-usb-v6.h"
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Dphy-qcom-qmp-pcie.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
17 #include <linux/phy/pcie.h>
18 #include <linux/phy/phy.h>
25 #include <dt-bindings/phy/phy-qcom-qmp.h>
27 #include "phy-qcom-qmp-common.h"
29 #include "phy-qcom-qmp.h"
30 #include "phy-qcom-qmp-pcs-misc-v3.h"
31 #include "phy-qcom-qmp-pcs-pcie-v4.h"
32 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
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/linux-6.14.4/drivers/net/phy/
Dphylink.c1 // SPDX-License-Identifier: GPL-2.0
3 * phylink models the MAC to optional PHY connection, supporting
4 * technologies such as SFP cages where the PHY is hot-pluggable.
15 #include <linux/phy.h>
44 * struct phylink - internal data type for phylink
51 struct phylink_pcs *pcs; member
61 u8 link_port; /* The current non-phy ethtool port */
103 if ((pl)->config->type == PHYLINK_NETDEV) \
104 netdev_printk(level, (pl)->netdev, fmt, ##__VA_ARGS__); \
105 else if ((pl)->config->type == PHYLINK_DEV) \
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Dqt2025.rs1 // SPDX-License-Identifier: GPL-2.0
5 //! Applied Micro Circuits Corporation QT2025 PHY driver
8 //! and firmware can be downloaded on the EN-9320SFP+ support site.
10 //! The QT2025 PHY integrates an Intel 8051 micro-controller.
15 use kernel::net::phy::{
26 phy::DeviceId::new_with_driver::<PhyQT2025>(),
30 description: "AMCC QT2025 PHY driver",
32 firmware: ["qt2025-2.0.3.3.fw"],
40 const PHY_DEVICE_ID: phy::DeviceId = phy::DeviceId::new_with_exact_mask(0x0043a400);
42 fn probe(dev: &mut phy::Device) -> Result<()> { in probe()
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/linux-6.14.4/include/linux/
Dphylink.h4 #include <linux/phy.h>
23 MLO_AN_PHY = 0, /* Conventional PHY */
24 MLO_AN_FIXED, /* Fixed-link mode */
25 MLO_AN_INBAND, /* In-band protocol */
27 /* PCS "negotiation" mode.
28 * PHYLINK_PCS_NEG_NONE - protocol has no inband capability
29 * PHYLINK_PCS_NEG_OUTBAND - some out of band or fixed link setting
30 * PHYLINK_PCS_NEG_INBAND_DISABLED - inband mode disabled, e.g.
31 * 1000base-X with autoneg off
32 * PHYLINK_PCS_NEG_INBAND_ENABLED - inband mode enabled
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/linux-6.14.4/arch/arm64/boot/dts/freescale/
Dtqmls1088a-mbls10xxa-mc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (c) 2018-2023 TQ-Systems GmbH <[email protected]-group.com>,
4 * D-82229 Seefeld, Germany.
10 #include <dt-bindings/net/ti-dp83867.h>
15 i2c-bus = <&sfp1_i2c>;
16 mod-def0-gpios = <&gpioexp2 2 GPIO_ACTIVE_LOW>;
17 los-gpios = <&gpioexp2 3 GPIO_ACTIVE_HIGH>;
18 tx-fault-gpios = <&gpioexp2 0 GPIO_ACTIVE_HIGH>;
19 tx-disable-gpios = <&gpioexp2 1 GPIO_ACTIVE_HIGH>;
24 i2c-bus = <&sfp2_i2c>;
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Dfsl-ls1088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2017-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
23 pcs-handle = <&pcs2>;
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
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Dfsl-ls1088a-ten64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on fsl-ls1088a-rdb.dts
5 * Copyright 2017-2020 NXP
6 * Copyright 2019-2021 Traverse Technologies
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
28 stdout-path = "serial0:115200n8";
32 compatible = "gpio-keys";
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/linux-6.14.4/Documentation/networking/
Dsfp-phylink.rst1 .. SPDX-License-Identifier: GPL-2.0
10 phylink is a mechanism to support hot-pluggable networking modules
11 directly connected to a MAC without needing to re-initialise the
12 adapter on hot-plug events.
14 phylink supports conventional phylib-based setups, fixed link setups
23 1. PHY mode
25 In PHY mode, we use phylib to read the current link settings from
26 the PHY, and pass them to the MAC driver. We expect the MAC driver
32 Fixed mode is the same as PHY mode as far as the MAC driver is
35 3. In-band mode
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/linux-6.14.4/Documentation/devicetree/bindings/net/
Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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Dfsl,fman-mdio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <[email protected]>
13 The MDIO is a bus to which the PHY devices are connected.
18 - fsl,fman-mdio
19 - fsl,fman-xmdio
20 - fsl,fman-memac-mdio
22 Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
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Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <[email protected]>
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
31 local-mac-address property.
32 $ref: /schemas/types.yaml#/definitions/uint8-array
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Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 provides connectivity to an external ethernet PHY supporting different
22 - Radhey Shyam Pandey <[email protected]>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
35 axistream-connected is specified, in which case the reg
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Dfsl,fman-dtsec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Madalin Bucur <[email protected]>
15 10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller
22 - fsl,fman-dtsec
23 - fsl,fman-xgec
24 - fsl,fman-memac
26 cell-index:
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/linux-6.14.4/drivers/net/dsa/sja1105/
Dsja1105_mdio.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/pcs/pcs-xpcs.h>
10 int sja1105_pcs_mdio_read_c45(struct mii_bus *bus, int phy, int mmd, int reg) in sja1105_pcs_mdio_read_c45() argument
12 struct sja1105_mdio_private *mdio_priv = bus->priv; in sja1105_pcs_mdio_read_c45()
13 struct sja1105_private *priv = mdio_priv->priv; in sja1105_pcs_mdio_read_c45()
35 int sja1105_pcs_mdio_write_c45(struct mii_bus *bus, int phy, int mmd, in sja1105_pcs_mdio_write_c45() argument
38 struct sja1105_mdio_private *mdio_priv = bus->priv; in sja1105_pcs_mdio_write_c45()
39 struct sja1105_private *priv = mdio_priv->priv; in sja1105_pcs_mdio_write_c45()
47 return -EINVAL; in sja1105_pcs_mdio_write_c45()
52 int sja1110_pcs_mdio_read_c45(struct mii_bus *bus, int phy, int mmd, int reg) in sja1110_pcs_mdio_read_c45() argument
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/linux-6.14.4/drivers/net/fddi/skfp/
Dpcmplc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
67 #define GO_STATE(x) (mib->fddiPORTPCMState = (x)|AFLAG)
68 #define ACTIONS_DONE() (mib->fddiPORTPCMState &= ~AFLAG)
109 * PCL-S control register
110 * this register in the PLC-S controls the scrambling parameters
121 * PCL-S control register
122 * this register in the PLC-S controls the scrambling parameters
152 #define PLC_MS(m) ((int)((0x10000L-(m*100000L/2048))))
191 static void pcm_fsm(struct s_smc *smc, struct s_phy *phy, int cmd);
192 static void pc_rcode_actions(struct s_smc *smc, int bit, struct s_phy *phy);
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/linux-6.14.4/drivers/net/ethernet/microchip/lan966x/
Dlan966x_phylink.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/phy/phy.h>
14 struct lan966x_port *port = netdev_priv(to_net_dev(config->dev)); in lan966x_phylink_mac_select()
16 return &port->phylink_pcs; in lan966x_phylink_mac_select()
29 struct lan966x_port *port = netdev_priv(to_net_dev(config->dev)); in lan966x_phylink_mac_prepare()
33 if (port->serdes) { in lan966x_phylink_mac_prepare()
34 err = phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET, in lan966x_phylink_mac_prepare()
37 netdev_err(to_net_dev(config->dev), in lan966x_phylink_mac_prepare()
47 struct phy_device *phy, in lan966x_phylink_mac_link_up() argument
53 struct lan966x_port *port = netdev_priv(to_net_dev(config->dev)); in lan966x_phylink_mac_link_up()
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/linux-6.14.4/drivers/net/dsa/mv88e6xxx/
Dpcs-639x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell 88E6352 family SERDES PCS support
16 #include "phy.h"
36 err = mdiodev_c45_read(&mpcs->mdio, MDIO_MMD_PHYXS, regnum); in mv88e639x_read()
47 return mdiodev_c45_write(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, val); in mv88e639x_write()
53 return mdiodev_c45_modify(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, mask, in mv88e639x_modify()
60 return mdiodev_c45_modify_changed(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, in mv88e639x_modify_changed()
74 mpcs->mdio.dev.parent = dev; in mv88e639x_pcs_alloc()
75 mpcs->mdio.bus = bus; in mv88e639x_pcs_alloc()
76 mpcs->mdio.addr = addr; in mv88e639x_pcs_alloc()
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/linux-6.14.4/drivers/net/ethernet/freescale/dpaa2/
Ddpaa2-mac.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 #include <linux/pcs-lynx.h>
6 #include <linux/phy/phy.h>
9 #include "dpaa2-eth.h"
10 #include "dpaa2-mac.h"
23 if (mac->ver_major == ver_major) in dpaa2_mac_cmp_ver()
24 return mac->ver_minor - ver_minor; in dpaa2_mac_cmp_ver()
25 return mac->ver_major - ver_major; in dpaa2_mac_cmp_ver()
30 mac->features = 0; in dpaa2_mac_detect_features()
34 mac->features |= DPAA2_MAC_FEATURE_PROTOCOL_CHANGE; in dpaa2_mac_detect_features()
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/linux-6.14.4/drivers/net/dsa/b53/
Db53_serdes.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Northstar Plus switch SerDes/SGMII PHY main logic
12 #include <linux/phy.h>
20 static inline struct b53_pcs *pcs_to_b53_pcs(struct phylink_pcs *pcs) in pcs_to_b53_pcs() argument
22 return container_of(pcs, struct b53_pcs, pcs); in pcs_to_b53_pcs()
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
68 static int b53_serdes_config(struct phylink_pcs *pcs, unsigned int neg_mode, in b53_serdes_config() argument
73 struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev; in b53_serdes_config()
74 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_config()
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