Lines Matching +full:pcs +full:- +full:phy

1 // SPDX-License-Identifier: GPL-2.0
5 //! Applied Micro Circuits Corporation QT2025 PHY driver
8 //! and firmware can be downloaded on the EN-9320SFP+ support site.
10 //! The QT2025 PHY integrates an Intel 8051 micro-controller.
15 use kernel::net::phy::{
26         phy::DeviceId::new_with_driver::<PhyQT2025>(),
30     description: "AMCC QT2025 PHY driver",
32     firmware: ["qt2025-2.0.3.3.fw"],
40     const PHY_DEVICE_ID: phy::DeviceId = phy::DeviceId::new_with_exact_mask(0x0043a400);
42     fn probe(dev: &mut phy::Device) -> Result<()> {  in probe()
50         // `MICRO_RESETN`: hold the micro-controller in reset while configuring.  in probe()
52         // `SREFCLK_FREQ`: configure clock frequency of the micro-controller.  in probe()
59         // 3.41 5/10/25GBASE-R PCS test pattern seed B) for something else.  in probe()
61         dev.write(C45::new(Mmd::PCS, 0x0026), 0x0e00)?;  in probe()
62         dev.write(C45::new(Mmd::PCS, 0x0027), 0x0893)?;  in probe()
63         dev.write(C45::new(Mmd::PCS, 0x0028), 0xa528)?;  in probe()
64         dev.write(C45::new(Mmd::PCS, 0x0029), 0x0003)?;  in probe()
67         // `MICRO_RESETN`: release the micro-controller from the reset state.  in probe()
69         // The micro-controller will start running from the boot ROM.  in probe()
70         dev.write(C45::new(Mmd::PCS, 0xe854), 0x00c0)?;  in probe()
72         let fw = Firmware::request(c_str!("qt2025-2.0.3.3.fw"), dev.as_ref())?;  in probe()
78         // The first 16kB of memory is located in the address range 3.8000h - 3.BFFFh.  in probe()
79         // The next 8kB of memory is located at 4.8000h - 4.9FFFh.  in probe()
81         let mut dst_mmd = Mmd::PCS;  in probe()
93         // The micro-controller will start running from SRAM.  in probe()
94         dev.write(C45::new(Mmd::PCS, 0xe854), 0x0040)?;  in probe()
100     fn read_status(dev: &mut phy::Device) -> Result<u16> {  in read_status()