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/linux-6.14.4/Documentation/devicetree/bindings/iommu/
Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM System MMU Architecture Implementation
10 - Will Deacon <[email protected]>
11 - Robin Murphy <[email protected]>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
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/linux-6.14.4/drivers/iommu/arm/arm-smmu/
Darm-smmu-impl.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #define pr_fmt(fmt) "arm-smmu: " fmt
10 #include "arm-smmu.h"
44 /* Since we don't care for sGFAR, we can do without 64-bit accessors */
65 cs->id_base = atomic_fetch_add(smmu->num_context_banks, &context_count); in cavium_cfg_probe()
66 dev_notice(smmu->dev, "\tenabling workaround for Cavium erratum 27704\n"); in cavium_cfg_probe()
74 struct cavium_smmu *cs = container_of(smmu_domain->smmu, in cavium_init_context()
77 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2) in cavium_init_context()
78 smmu_domain->cfg.vmid += cs->id_base; in cavium_init_context()
80 smmu_domain->cfg.asid += cs->id_base; in cavium_init_context()
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Darm-smmu-nvidia.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2019-2020 NVIDIA CORPORATION. All rights reserved.
12 #include "arm-smmu.h"
15 * Tegra194 has three ARM MMU-500 Instances.
18 * non-isochronous HW devices.
23 * memory client. This is necessary to allow for use-case such as seamlessly
52 return nvidia_smmu->bases[inst] + (page << smmu->pgshift); in nvidia_smmu_page()
69 for (i = 0; i < nvidia->num_instances; i++) { in nvidia_smmu_write_reg()
90 for (i = 0; i < nvidia->num_instances; i++) { in nvidia_smmu_write_reg64()
108 for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) { in nvidia_smmu_tlb_sync()
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Darm-smmu.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * - SMMUv1 and v2 implementations
11 * - Stream-matching and stream-indexing
12 * - v7/v8 long-descriptor format
13 * - Non-secure access to the SMMU
14 * - Context fault reporting
15 * - Extended Stream ID (16 bit)
18 #define pr_fmt(fmt) "arm-smmu: " fmt
24 #include <linux/dma-mapping.h>
41 #include "arm-smmu.h"
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/linux-6.14.4/drivers/iommu/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 # The IOVA library may also be used by non-IOMMU_API users
16 depends on MMU
40 sizes at both stage-1 and stage-2, as well as address spaces
41 up to 48-bits in size.
47 Enable self-tests for LPAE page table allocator. This performs
48 a series of page-table consistency checks during boot.
57 Enable support for the ARM Short-descriptor pagetable format.
58 This supports 32-bit virtual and physical addresses mapped using
59 2-level tables with 4KB pages/1MB sections, and contiguous entries
[all …]
/linux-6.14.4/arch/arm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
10 select ARCH_HAS_CPU_FINALIZE_INIT if MMU
14 select ARCH_HAS_DEBUG_VIRTUAL if MMU
15 select ARCH_HAS_DMA_ALLOC if MMU
28 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
29 select ARCH_HAS_STRICT_MODULE_RWX if MMU
32 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
49 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
54 select BUILDTIME_TABLE_SORT if MMU
60 select DMA_GLOBAL_POOL if !MMU
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/linux-6.14.4/drivers/gpu/drm/gma500/
Dpsb_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2007-2011, Intel Corporation.
45 * to the different groups of PowerVR 5-series chip designs
49 * PowerVR SGX535 - Poulsbo - Intel GMA 500, Intel Atom Z5xx
50 * PowerVR SGX535 - Moorestown - Intel GMA 600
51 * PowerVR SGX535 - Oaktrail - Intel GMA 600, Intel Atom Z6xx, E6xx
52 * PowerVR SGX545 - Cedartrail - Intel GMA 3600, Intel Atom D2500, N2600
53 * PowerVR SGX545 - Cedartrail - Intel GMA 3650, Intel Atom D2550, D2700,
98 * psb_spank - reset the 2D engine
124 PSB_WSGX32(dev_priv->gtt.gatt_start, PSB_CR_BIF_TWOD_REQ_BASE); in psb_spank()
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/linux-6.14.4/Documentation/devicetree/bindings/cpu/
Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <[email protected]>
11 - Anup Patel <[email protected]>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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/linux-6.14.4/arch/alpha/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
43 The Alpha is a 64-bit general-purpose processor designed and
45 now Hewlett-Packard. The Alpha Linux project has a home page at
51 config MMU config
92 Alcor/Alpha-XLT AS 600, AS 500, XL-300, XL-366
94 LX164 AlphaPC164-LX
95 Miata Personal Workstation 433/500/600 a/au
101 Ruffian RPX164-2, AlphaPC164-UX, AlphaPC164-BX
102 SX164 AlphaPC164-SX
119 bool "Alcor/Alpha-XLT"
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/linux-6.14.4/drivers/cpufreq/
Dpmac32-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <[email protected]>
42 * init/main.c to make it non-init before enabling DEBUG_FREQ
101 * core cpufreq framework's own calculation. in debug_calc_bogomips()
198 /* Delay is way too big but it's ok, we schedule */ in gpios_set_cpu_speed()
220 /* Delay is way too big but it's ok, we schedule */ in gpios_set_cpu_speed()
255 * the above didn't re-enable the DEC */ in pmu_set_cpu_speed()
271 save_l3cr = _get_L3CR(); /* (returns -1 if not available) */ in pmu_set_cpu_speed()
272 save_l2cr = _get_L2CR(); /* (returns -1 if not available) */ in pmu_set_cpu_speed()
299 /* Restore userland MMU context */ in pmu_set_cpu_speed()
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/linux-6.14.4/arch/sparc/include/asm/
Dfloppy_32.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 1995 David S. Miller ([email protected])
76 #if 0 /* P3: added by Alain, these cause a MMU corruption. 19960524 XXX */
100 #define CROSS_64KB(a,s) (0) argument
106 sun_fdc->dor_82077 = value; in sun_set_dor()
111 return sun_fdc->dir_82077; in sun_read_dir()
122 return sun_fdc->status_82072 & ~STATUS_DMA; in sun_82072_fd_inb()
124 return sun_fdc->data_82072; in sun_82072_fd_inb()
142 sun_fdc->data_82072 = value; in sun_82072_fd_outb()
145 sun_fdc->dcr_82072 = value; in sun_82072_fd_outb()
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/linux-6.14.4/drivers/gpu/drm/panfrost/
Dpanfrost_job.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-resv.h>
25 #define JOB_TIMEOUT_MS 500
27 #define job_write(dev, reg, data) writel(data, dev->iomem + (reg))
28 #define job_read(dev, reg) readl(dev->iomem + (reg))
71 switch (f->queue) { in panfrost_fence_get_timeline_name()
73 return "panfrost-js-0"; in panfrost_fence_get_timeline_name()
75 return "panfrost-js-1"; in panfrost_fence_get_timeline_name()
77 return "panfrost-js-2"; in panfrost_fence_get_timeline_name()
91 struct panfrost_job_slot *js = pfdev->js; in panfrost_fence_create()
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/linux-6.14.4/drivers/bus/
Darm-cci.c17 #include <linux/arm-cci.h>
49 {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },
52 { .compatible = "arm,cci-500", },
53 { .compatible = "arm,cci-550", },
59 OF_DEV_AUXDATA("arm,cci-400-pmu", 0, NULL, &cci_ctrl_base),
60 OF_DEV_AUXDATA("arm,cci-400-pmu,r0", 0, NULL, &cci_ctrl_base),
61 OF_DEV_AUXDATA("arm,cci-400-pmu,r1", 0, NULL, &cci_ctrl_base),
62 OF_DEV_AUXDATA("arm,cci-500-pmu,r0", 0, NULL, &cci_ctrl_base),
63 OF_DEV_AUXDATA("arm,cci-550-pmu,r0", 0, NULL, &cci_ctrl_base),
67 #define DRIVER_NAME "ARM-CCI"
[all …]
/linux-6.14.4/drivers/accel/ivpu/
Divpu_hw_ip.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-2024 Intel Corporation
87 return -EIO; in host_ss_noc_qreqn_check_37xx()
97 return -EIO; in host_ss_noc_qreqn_check_40xx()
115 return -EIO; in host_ss_noc_qacceptn_check_37xx()
125 return -EIO; in host_ss_noc_qacceptn_check_40xx()
143 return -EIO; in host_ss_noc_qdeny_check_37xx()
153 return -EIO; in host_ss_noc_qdeny_check_40xx()
172 return -EIO; in top_noc_qrenqn_check_37xx()
183 return -EIO; in top_noc_qrenqn_check_40xx()
[all …]
/linux-6.14.4/Documentation/virt/uml/
Duser_mode_linux_howto_v2.rst1 .. SPDX-License-Identifier: GPL-2.0
25 Most OSes today have built-in support for a number of "fake"
27 User Mode Linux takes this concept to the ultimate extreme - there
30 concepts which map onto something provided by the host - files, sockets,
36 The UML kernel is just a process running on Linux - same as any other
45 results in a number of advantages and disadvantages of UML over let's say
57 * You can run a usermode kernel as a non-root user (you may need to
74 * It's fun.
99 This is extremely easy on Debian - you can do it using debootstrap. It is
100 also easy on OpenWRT - the build process can build UML images. All other
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/linux-6.14.4/drivers/accel/habanalabs/goya/
Dgoya.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2022 HabanaLabs, Ltd.
9 #include "../include/hw_ip/mmu/mmu_general.h"
10 #include "../include/hw_ip/mmu/mmu_v1_0.h"
23 * - Range registers (When MMU is enabled, DMA RR does NOT protect host)
24 * - MMU
27 * - Range registers (protect the first 512MB)
28 * - MMU (isolation between users)
31 * - Range registers
32 * - Protection bits
[all …]
/linux-6.14.4/drivers/clocksource/
Dhyperv_timer.c1 // SPDX-License-Identifier: GPL-2.0
5 * provided by the Hyper-V hypervisor to guest VMs, as described
6 * in the Hyper-V Top Level Functional Spec (TLFS). This driver
36 * mechanism is used when running on older versions of Hyper-V
37 * that don't support Direct Mode. While Hyper-V provides
38 * four stimer's per CPU, Linux uses only stimer0.
44 * However, for legacy versions of Hyper-V when Direct Mode
51 static int stimer0_irq = -1;
64 ce->event_handler(ce); in hv_stimer0_isr()
70 * per-cpu interrupts, which also implies Direct Mode.
[all …]
/linux-6.14.4/drivers/gpu/drm/nouveau/nvkm/engine/device/
Dpci.c17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
846 { 0x00fd, "Quadro FX 330/Quadro NVS 280 PCI-E" },
888 { 0x0173, "GeForce4 MX 440-SE" },
896 { 0x017c, "Quadro4 500 GoGL" },
930 { 0x0202, "GeForce3 Ti 500" },
937 { 0x0222, "GeForce 6200 A-LE" },
942 { 0x0245, "Quadro NVS 210S / GeForce 6150LE" },
997 { 0x032b, "Quadro FX 500/FX 600" },
1126 { 0x0630, "GeForce 9700 S" },
1168 { 0x06df, "Tesla M2070-Q" },
[all …]
/linux-6.14.4/drivers/gpu/drm/msm/adreno/
Da6xx_gpu.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
15 #include <linux/soc/qcom/llcc-qcom.h>
25 if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu)) in _a6xx_check_idle()
44 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n", in a6xx_idle()
45 gpu->name, __builtin_return_address(0), in a6xx_idle()
62 if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) { in update_shadow_rptr()
78 spin_lock_irqsave(&ring->preempt_lock, flags); in a6xx_flush()
81 ring->cur = ring->next; in a6xx_flush()
88 if (a6xx_gpu->cur_ring == ring) in a6xx_flush()
[all …]
/linux-6.14.4/drivers/gpu/drm/sprd/
Dsprd_dpu.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/dma-buf.h>
56 /* MMU control registers */
130 struct dpu_context *ctx = &dpu->ctx; in dpu_wait_stop_done()
133 if (ctx->stopped) in dpu_wait_stop_done()
136 rc = wait_event_interruptible_timeout(ctx->wait_queue, ctx->evt_stop, in dpu_wait_stop_done()
137 msecs_to_jiffies(500)); in dpu_wait_stop_done()
138 ctx->evt_stop = false; in dpu_wait_stop_done()
140 ctx->stopped = true; in dpu_wait_stop_done()
143 drm_err(dpu->drm, "dpu wait for stop done time out!\n"); in dpu_wait_stop_done()
[all …]
/linux-6.14.4/drivers/gpu/drm/etnaviv/
Detnaviv_gpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015-2018 Etnaviv Project
9 #include <linux/dma-fence.h>
10 #include <linux/dma-mapping.h>
32 { .name = "etnaviv-gpu,2d" },
42 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_get_param()
46 *value = gpu->identity.model; in etnaviv_gpu_get_param()
50 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
54 *value = gpu->identity.features; in etnaviv_gpu_get_param()
58 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param()
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/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dqcm2290.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
9 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
10 #include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interconnect/qcom,qcm2290.h>
[all …]
/linux-6.14.4/kernel/trace/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 API, which will be used by other function-entry hooking
27 See Documentation/trace/ftrace-design.rst
32 See Documentation/trace/ftrace-design.rst
45 See Documentation/trace/ftrace-design.rst
80 See Documentation/trace/ftrace-design.rst
85 See Documentation/trace/ftrace-design.rst
90 Arch supports the gcc options -pg with -mfentry
95 Arch supports the gcc options -pg with -mrecord-mcount and -nop-mcount
100 Arch supports objtool --mcount
[all …]
/linux-6.14.4/arch/x86/kvm/vmx/
Dvmx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
31 #include <linux/entry-kvm.h>
50 #include <asm/spec-ctrl.h>
62 #include "mmu.h"
77 MODULE_DESCRIPTION("KVM support for VMX (Intel VT-x) extensions");
140 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
192 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
208 /* Default doubles per-vcpu window every exit. */
[all …]
/linux-6.14.4/drivers/usb/gadget/udc/
Dat91_udc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * at91_udc -- driver for at91-series USB peripheral controller
33 #include <linux/mfd/syscon/atmel-matrix.h>
39 * This controller is simple and PIO-only. It's used in many AT91-series
40 * full speed USB controllers, including the at91rm9200 (arm920T, with MMU),
41 * at91sam926x (arm926ejs, with MMU), and several no-mmu versions.
47 * The pullup is most important (so it's integrated on sam926x parts). It
76 EP_INFO("ep3-int",
91 __raw_readl((udc)->udp_baseaddr + (reg))
93 __raw_writel((val), (udc)->udp_baseaddr + (reg))
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