Searched refs:DFSDM_FLTICR_CLRSCDF_Pos (Results 1 – 10 of 10) sorted by relevance
1384 filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); in HAL_DFSDM_ChannelPollForScd()1405 DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); in HAL_DFSDM_ChannelPollForScd()1454 filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); in HAL_DFSDM_ChannelScdStop()1456 DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); in HAL_DFSDM_ChannelScdStop()1579 filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); in HAL_DFSDM_ChannelScdStop_IT()1584 DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); in HAL_DFSDM_ChannelScdStop_IT()3523 hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); in HAL_DFSDM_IRQHandler()3550 hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); in HAL_DFSDM_IRQHandler()
1038 DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); in HAL_DFSDM_ChannelPollForScd()1071 DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); in HAL_DFSDM_ChannelScdStop()1163 DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); in HAL_DFSDM_ChannelScdStop_IT()3067 hdfsdm_filter->Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); in HAL_DFSDM_IRQHandler()
5451 #define DFSDM_FLTICR_CLRSCDF_Pos (24U) macro5452 #define DFSDM_FLTICR_CLRSCDF_Msk (0xFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0x0F000000 */5555 #define DFSDM_FLTICR_CLRSCSDF_Pos DFSDM_FLTICR_CLRSCDF_Pos
5511 #define DFSDM_FLTICR_CLRSCDF_Pos (24U) macro5512 #define DFSDM_FLTICR_CLRSCDF_Msk (0xFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0x0F000000 */5615 #define DFSDM_FLTICR_CLRSCSDF_Pos DFSDM_FLTICR_CLRSCDF_Pos
5509 #define DFSDM_FLTICR_CLRSCDF_Pos (24U) macro5510 #define DFSDM_FLTICR_CLRSCDF_Msk (0xFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0x0F000000 */5613 #define DFSDM_FLTICR_CLRSCSDF_Pos DFSDM_FLTICR_CLRSCDF_Pos
5805 #define DFSDM_FLTICR_CLRSCDF_Pos (24U) macro5806 #define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */5911 #define DFSDM_FLTICR_CLRSCSDF_Pos DFSDM_FLTICR_CLRSCDF_Pos
5841 #define DFSDM_FLTICR_CLRSCDF_Pos (24U) macro5842 #define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */5947 #define DFSDM_FLTICR_CLRSCSDF_Pos DFSDM_FLTICR_CLRSCDF_Pos
5505 #define DFSDM_FLTICR_CLRSCDF_Pos (24U) macro5506 #define DFSDM_FLTICR_CLRSCDF_Msk (0xFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0x0F000000 */5609 #define DFSDM_FLTICR_CLRSCSDF_Pos DFSDM_FLTICR_CLRSCDF_Pos
6171 #define DFSDM_FLTICR_CLRSCDF_Pos (24U) macro6172 #define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */
6570 #define DFSDM_FLTICR_CLRSCDF_Pos (24U) macro6571 #define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */