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Searched refs:BSP_CLOCKS_CLOCK_DISABLED (Results 1 – 3 of 3) sorted by relevance

/btstack/port/renesas-ek-ra6m4a-da14531/e2-project/ra_gen/
H A Dbsp_clock_cfg.h11 #define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL2 Disabled */
15 #define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
16 #define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* UCLK Disabled */
17 #define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
/btstack/port/renesas-ek-ra6m4a-da14531/e2-project/ra/fsp/src/bsp/mcu/all/
H A Dbsp_clocks.c1116 #if BSP_FEATURE_CGC_HAS_PLL2 && BSP_CFG_PLL2_SOURCE != BSP_CLOCKS_CLOCK_DISABLED in bsp_clock_init()
1220 #if BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_CLOCK_DISABLED in bsp_clock_init()
1232 #if BSP_CFG_UCK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED in bsp_clock_init()
1284 #if BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK && BSP_CFG_OCTA_SOURCE != BSP_CLOCKS_CLOCK_DISABLED in bsp_clock_init()
1294 #if BSP_FEATURE_BSP_HAS_CANFD_CLOCK && (BSP_CFG_CANFDCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) && \ in bsp_clock_init()
1316 #if BSP_FEATURE_BSP_HAS_SCISPI_CLOCK && (BSP_CFG_SCISPICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) in bsp_clock_init()
1337 #if BSP_FEATURE_BSP_HAS_GPT_CLOCK && (BSP_CFG_GPTCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) in bsp_clock_init()
1358 #if BSP_FEATURE_BSP_HAS_IIC_CLOCK && (BSP_CFG_IICCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) in bsp_clock_init()
H A Dbsp_clocks.h226 #define BSP_CLOCKS_CLOCK_DISABLED (0xFFU) macro