1*c3086949SMatthias Ringwald /* generated configuration header file - do not edit */ 2*c3086949SMatthias Ringwald #ifndef BSP_CLOCK_CFG_H_ 3*c3086949SMatthias Ringwald #define BSP_CLOCK_CFG_H_ 4*c3086949SMatthias Ringwald #define BSP_CFG_CLOCKS_SECURE (0) 5*c3086949SMatthias Ringwald #define BSP_CFG_CLOCKS_OVERRIDE (0) 6*c3086949SMatthias Ringwald #define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ 7*c3086949SMatthias Ringwald #define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ 8*c3086949SMatthias Ringwald #define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ 9*c3086949SMatthias Ringwald #define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ 10*c3086949SMatthias Ringwald #define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_25_0 /* PLL Mul x25.0 */ 11*c3086949SMatthias Ringwald #define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL2 Disabled */ 12*c3086949SMatthias Ringwald #define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ 13*c3086949SMatthias Ringwald #define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL2 Mul x20.0 */ 14*c3086949SMatthias Ringwald #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ 15*c3086949SMatthias Ringwald #define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ 16*c3086949SMatthias Ringwald #define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* UCLK Disabled */ 17*c3086949SMatthias Ringwald #define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ 18*c3086949SMatthias Ringwald #define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ 19*c3086949SMatthias Ringwald #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ 20*c3086949SMatthias Ringwald #define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ 21*c3086949SMatthias Ringwald #define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ 22*c3086949SMatthias Ringwald #define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ 23*c3086949SMatthias Ringwald #define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ 24*c3086949SMatthias Ringwald #define BSP_CFG_BCLK_OUTPUT (2) /* BCLK/2 */ 25*c3086949SMatthias Ringwald #define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ 26*c3086949SMatthias Ringwald #define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ 27*c3086949SMatthias Ringwald #define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ 28*c3086949SMatthias Ringwald #define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */ 29*c3086949SMatthias Ringwald #endif /* BSP_CLOCK_CFG_H_ */ 30