Home
last modified time | relevance | path

Searched refs:xdn (Results 1 – 8 of 8) sorted by relevance

/aosp_15_r20/external/llvm/test/CodeGen/Mips/
H A Dfp16instrinsmc.ll9 @xdn = global double 0xC0311F9ADD373963, align 8
99 %0 = load double, double* @xdn, align 8
/aosp_15_r20/external/vixl/src/aarch64/
H A Dassembler-aarch64.h3993 void decb(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
3996 void decd(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
4002 void dech(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
4014 void decw(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
4498 void incb(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
4501 void incd(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
4507 void inch(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
4519 void incw(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
5382 void sqdecp(const Register& xdn, const PRegisterWithLaneSize& pg);
5449 void sqincp(const Register& xdn, const PRegisterWithLaneSize& pg);
H A Dmacro-assembler-aarch64.h5748 void Sqdecp(const Register& xdn, in Sqdecp() argument
5753 sqdecp(xdn, pg, wdn); in Sqdecp()
5755 void Sqdecp(const Register& xdn, const PRegisterWithLaneSize& pg) { in Sqdecp() argument
5758 sqdecp(xdn, pg); in Sqdecp()
5837 void Sqincp(const Register& xdn, in Sqincp() argument
5842 sqincp(xdn, pg, wdn); in Sqincp()
5844 void Sqincp(const Register& xdn, const PRegisterWithLaneSize& pg) { in Sqincp() argument
5847 sqincp(xdn, pg); in Sqincp()
H A Dassembler-sve-aarch64.cc2087 void Assembler::sqdecp(const Register& xdn, const PRegisterWithLaneSize& pg) { in sqdecp() argument
2094 VIXL_ASSERT(xdn.IsX()); in sqdecp()
2096 Emit(SQDECP_r_p_r_x | SVESize(pg) | Rd(xdn) | Rx<8, 5>(pg)); in sqdecp()
2126 void Assembler::sqincp(const Register& xdn, const PRegisterWithLaneSize& pg) { in sqincp() argument
2133 VIXL_ASSERT(xdn.IsX()); in sqincp()
2135 Emit(SQINCP_r_p_r_x | SVESize(pg) | Rd(xdn) | Rx<8, 5>(pg)); in sqincp()
/aosp_15_r20/external/vixl/doc/aarch64/
H A Dsupported-instructions-aarch64.md7160 void decb(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1)
7167 void decd(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1)
7181 void dech(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1)
7209 void decw(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1)
8276 void incb(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1)
8283 void incd(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1)
8297 void inch(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1)
8325 void incw(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1)
10359 void sqdecp(const Register& xdn, const PRegisterWithLaneSize& pg)
10608 void sqincp(const Register& xdn, const PRegisterWithLaneSize& pg)
/aosp_15_r20/frameworks/av/media/libstagefright/httplive/fuzzer/corpus/
H A Dmeta2329 …�؋�i�Q�<�ua�hgңP�3�XZ�$��wP ����D����=��m�{��s7�G��o�5.�ܲ�� ���x�u�xdn��j�Jl�����,�/…
37743 …�؋�i�Q�<�ua�hgңP�3�XZ�$��wP ����D����=��m�{��s7�G��o�5.�ܲ�� ���x�u�xdn��j�Jl�����,�/…
H A Dindex142331 …ÑQÒ<ŠuaÙhgÒ£Pµ3üXZ$š–wP ¼™ãúDÞõæÆ=¯mÍ{ëæs7‰G›Õoþ5.‡Ü²€Ð ²Ã×x uãŸxdnÊ°jÿJlÿû’ ó±,Ô…
37745 …ÑQÒ<ŠuaÙhgÒ£Pµ3üXZ$š–wP ¼™ãúDÞõæÆ=¯mÍ{ëæs7‰G›Õoþ5.‡Ü²€Ð ²Ã×x uãŸxdnÊ°jÿJlÿû’ ó±,Ô…
H A Dmeta22371 …�؋�i�Q�<�ua�hgңP�3�XZ�$��wP ����D����=��m�{��s7�G��o�5.�ܲ�� ���x�u�xdn��j�Jl�����,�/…