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Searched refs:inline_push_constant_mask (Results 1 – 9 of 9) sorted by relevance

/aosp_15_r20/external/mesa3d/src/amd/vulkan/
H A Dradv_shader_args.c18 uint64_t inline_push_constant_mask; member
29 if (!info->inline_push_constant_mask) in allocate_inline_push_consts()
32 uint64_t mask = info->inline_push_constant_mask; in allocate_inline_push_consts()
51 user_sgpr_info->inline_push_constant_mask = mask; in allocate_inline_push_consts()
107 for (unsigned i = 0; i < util_bitcount64(user_sgpr_info->inline_push_constant_mask); i++) { in declare_global_input_sgprs()
110 args->ac.inline_push_const_mask = user_sgpr_info->inline_push_constant_mask; in declare_global_input_sgprs()
H A Dradv_pipeline_compute.c75 metadata->inline_push_const_mask = cs->info.inline_push_constant_mask; in radv_get_compute_shader_metadata()
116 cs_stage->info.inline_push_constant_mask = cs_stage->args.ac.inline_push_const_mask; in radv_compile_cs()
H A Dradv_pipeline_graphics.c2207 stages[MESA_SHADER_TESS_CTRL].info.inline_push_constant_mask = in radv_declare_pipeline_args()
2211 stages[MESA_SHADER_VERTEX].info.inline_push_constant_mask = in radv_declare_pipeline_args()
2212 stages[MESA_SHADER_TESS_CTRL].info.inline_push_constant_mask; in radv_declare_pipeline_args()
2224 stages[MESA_SHADER_GEOMETRY].info.inline_push_constant_mask = in radv_declare_pipeline_args()
2228 …stages[pre_stage].info.inline_push_constant_mask = stages[MESA_SHADER_GEOMETRY].info.inline_push_c… in radv_declare_pipeline_args()
2237 stages[i].info.inline_push_constant_mask = stages[i].args.ac.inline_push_const_mask; in radv_declare_pipeline_args()
2284 gs_copy_stage.info.inline_push_constant_mask = gs_copy_stage.args.ac.inline_push_const_mask; in radv_create_gs_copy_shader()
H A Dradv_shader_info.h81 uint64_t inline_push_constant_mask; member
H A Dradv_shader_info.c202 info->inline_push_constant_mask |= u_bit_consecutive64(start, size); in gather_push_constant_info()
961 info->inline_push_constant_mask = 0; in gather_shader_info_rt()
1805 dst_info->inline_push_constant_mask |= src_info->inline_push_constant_mask; in radv_nir_shader_info_merge()
H A Dradv_device_generated_commands.c2609 desc[i * 3 + 1] = pipeline->shaders[i]->info.inline_push_constant_mask; in radv_prepare_dgc()
2610 desc[i * 3 + 2] = pipeline->shaders[i]->info.inline_push_constant_mask >> 32; in radv_prepare_dgc()
H A Dradv_pipeline_rt.c384 stage->info.inline_push_constant_mask = stage->args.ac.inline_push_const_mask; in radv_rt_nir_to_asm()
H A Dradv_shader.c3176 info.inline_push_constant_mask = args.ac.inline_push_const_mask;
H A Dradv_cmd_buffer.c5908 const uint64_t mask = shader->info.inline_push_constant_mask; in radv_emit_all_inline_push_consts()