/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUInstructionSelector.cpp | 104 = TRI.getConstrainedRegClassForOperand(Dst, *MRI); in selectCOPY() 116 = TRI.getConstrainedRegClassForOperand(Src, *MRI); in selectCOPY() 140 TRI.getConstrainedRegClassForOperand(Dst, *MRI); in selectCOPY() 152 TRI.getConstrainedRegClassForOperand(Src, *MRI); in selectCOPY() 165 TRI.getConstrainedRegClassForOperand(MO, *MRI); in selectCOPY() 476 TRI.getConstrainedRegClassForOperand(MO, *MRI); in selectG_EXTRACT() 512 = TRI.getConstrainedRegClassForOperand(Src, *MRI); in selectG_MERGE_VALUES() 557 TRI.getConstrainedRegClassForOperand(Dst, *MRI); in selectG_UNMERGE_VALUES() 575 const TargetRegisterClass *RC = TRI.getConstrainedRegClassForOperand(MO, *MRI); in selectG_IMPLICIT_DEF() 1191 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); in selectG_SELECT() [all …]
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H A D | SIRegisterInfo.h | 267 getConstrainedRegClassForOperand(const MachineOperand &MO,
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H A D | SIRegisterInfo.cpp | 1815 SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO, in getConstrainedRegClassForOperand() function in SIRegisterInfo
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUInstructionSelector.cpp | 110 = TRI.getConstrainedRegClassForOperand(Dst, *MRI); in constrainCopyLikeIntrin() 112 = TRI.getConstrainedRegClassForOperand(Src, *MRI); in constrainCopyLikeIntrin() 133 = TRI.getConstrainedRegClassForOperand(Dst, *MRI); in selectCOPY() 145 = TRI.getConstrainedRegClassForOperand(Src, *MRI); in selectCOPY() 178 TRI.getConstrainedRegClassForOperand(Dst, *MRI); in selectCOPY() 190 TRI.getConstrainedRegClassForOperand(MO, *MRI); in selectCOPY() 501 TRI.getConstrainedRegClassForOperand(I.getOperand(0), *MRI); in selectG_EXTRACT() 607 = TRI.getConstrainedRegClassForOperand(Src, *MRI); in selectG_MERGE_VALUES() 655 TRI.getConstrainedRegClassForOperand(Dst, *MRI); in selectG_UNMERGE_VALUES() 821 const TargetRegisterClass *RC = TRI.getConstrainedRegClassForOperand(MO, *MRI); in selectG_IMPLICIT_DEF() [all …]
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H A D | SIRegisterInfo.h | 323 getConstrainedRegClassForOperand(const MachineOperand &MO,
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H A D | SIRegisterInfo.cpp | 3015 SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO, in getConstrainedRegClassForOperand() function in SIRegisterInfo
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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
H A D | Utils.cpp | 89 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); in constrainOperandRegClass()
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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
H A D | TargetRegisterInfo.h | 971 getConstrainedRegClassForOperand(const MachineOperand &MO, in getConstrainedRegClassForOperand() function
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/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/CodeGen/ |
D | TargetRegisterInfo.h | 1155 getConstrainedRegClassForOperand(const MachineOperand &MO, in getConstrainedRegClassForOperand() function
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/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/CodeGen/ |
D | TargetRegisterInfo.h | 1157 getConstrainedRegClassForOperand(const MachineOperand &MO, in getConstrainedRegClassForOperand() function
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/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/CodeGen/ |
D | TargetRegisterInfo.h | 1157 getConstrainedRegClassForOperand(const MachineOperand &MO, in getConstrainedRegClassForOperand() function
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/CodeGen/ |
H A D | TargetRegisterInfo.h | 1141 getConstrainedRegClassForOperand(const MachineOperand &MO, in getConstrainedRegClassForOperand() function
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/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/CodeGen/ |
D | TargetRegisterInfo.h | 1182 getConstrainedRegClassForOperand(const MachineOperand &MO, in getConstrainedRegClassForOperand() function
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/GlobalISel/ |
H A D | Utils.cpp | 126 OpRC, TRI.getConstrainedRegClassForOperand(RegMO, MRI))) in constrainOperandRegClass()
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