Home
last modified time | relevance | path

Searched refs:constrainOperandRegClass (Results 1 – 25 of 47) sorted by relevance

12

/aosp_15_r20/external/llvm/lib/Target/ARM/
H A DARMFastISel.cpp286 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_r()
309 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rr()
310 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rr()
337 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_ri()
364 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rri()
365 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rri()
532 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
605 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0); in ARMMaterializeGV()
681 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); in fastMaterializeAlloca()
1068 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1); in ARMEmitStore()
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/
H A DARMFastISel.cpp304 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_r()
326 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rr()
327 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rr()
353 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_ri()
509 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
582 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0); in ARMMaterializeGV()
659 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); in fastMaterializeAlloca()
1051 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1); in ARMEmitStore()
1127 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0); in ARMEmitStore()
1264 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); in SelectBranch()
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMFastISel.cpp309 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_r()
332 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rr()
333 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rr()
360 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_ri()
524 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
601 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0); in ARMMaterializeGV()
677 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); in fastMaterializeAlloca()
1066 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1); in ARMEmitStore()
1140 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0); in ARMEmitStore()
1277 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); in SelectBranch()
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp40 unsigned llvm::constrainOperandRegClass( in constrainOperandRegClass() function in llvm
70 unsigned llvm::constrainOperandRegClass( in constrainOperandRegClass() function in llvm
107 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass, in constrainOperandRegClass()
144 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), in constrainSelectedInstRegOperands()
H A DInstructionSelector.cpp44 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, in constrainOperandRegToRegClass()
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h57 unsigned constrainOperandRegClass(const MachineFunction &MF,
75 unsigned constrainOperandRegClass(const MachineFunction &MF,
/aosp_15_r20/external/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1789 unsigned FastISel::constrainOperandRegClass(const MCInstrDesc &II, unsigned Op, in constrainOperandRegClass() function in FastISel
1821 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
1843 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
1844 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
1868 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
1869 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
1870 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
1894 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
1917 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rii()
1961 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rri()
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp2023 unsigned FastISel::constrainOperandRegClass(const MCInstrDesc &II, unsigned Op, in constrainOperandRegClass() function in FastISel
2055 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
2077 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
2078 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
2102 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
2103 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
2104 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
2128 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
2151 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rii()
2195 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rri()
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1901 Register FastISel::constrainOperandRegClass(const MCInstrDesc &II, Register Op, in constrainOperandRegClass() function in FastISel
1932 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
1954 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
1955 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
1978 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
1979 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
1980 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
2005 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
2028 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rii()
2073 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rri()
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1141 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx)); in addLoadStoreOperands()
1143 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1344 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1345 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1389 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1431 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1432 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1476 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1477 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rx()
2102 SrcReg = constrainOperandRegClass(II, SrcReg, 0); in emitStoreRelease()
[all …]
H A DAArch64CallLowering.cpp911 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerTailCall()
997 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerCall()
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1142 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx)); in addLoadStoreOperands()
1144 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1333 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1334 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1378 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1419 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1420 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1463 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1464 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rx()
2073 SrcReg = constrainOperandRegClass(II, SrcReg, 0); in emitStoreRelease()
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/CodeGen/GlobalISel/
DUtils.h106 Register constrainOperandRegClass(const MachineFunction &MF,
125 Register constrainOperandRegClass(const MachineFunction &MF,
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h102 Register constrainOperandRegClass(const MachineFunction &MF,
121 Register constrainOperandRegClass(const MachineFunction &MF,
/aosp_15_r20/external/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1062 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx)); in addLoadStoreOperands()
1064 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1261 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1262 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1306 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1346 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1347 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1389 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1390 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rx()
2060 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs()); in emitStore()
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/CodeGen/GlobalISel/
DUtils.h107 Register constrainOperandRegClass(const MachineFunction &MF,
126 Register constrainOperandRegClass(const MachineFunction &MF,
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/CodeGen/GlobalISel/
DUtils.h107 Register constrainOperandRegClass(const MachineFunction &MF,
126 Register constrainOperandRegClass(const MachineFunction &MF,
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/CodeGen/GlobalISel/
DUtils.h107 Register constrainOperandRegClass(const MachineFunction &MF,
126 Register constrainOperandRegClass(const MachineFunction &MF,
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp53 Register llvm::constrainOperandRegClass( in constrainOperandRegClass() function in llvm
105 Register llvm::constrainOperandRegClass( in constrainOperandRegClass() function in llvm
148 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *OpRC, in constrainOperandRegClass()
185 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), MO, OpI); in constrainSelectedInstRegOperands()
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp218 constrainOperandRegClass(MF, *TRI, MRI, *TII, *RBI, II, II.getDesc(), in optimizeNZCVDefs()
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/
H A DX86FastISel.cpp217 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
642 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
3964 Register IndexReg = constrainOperandRegClass(Result->getDesc(), in tryToFoldLoadIntoMI()
3985 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrrr()
3986 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrrr()
3987 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrrr()
3988 Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3); in fastEmitInst_rrrr()
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86FastISel.cpp230 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
647 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
3961 unsigned IndexReg = constrainOperandRegClass(Result->getDesc(), in tryToFoldLoadIntoMI()
3984 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrrr()
3985 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrrr()
3986 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrrr()
3987 Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3); in fastEmitInst_rrrr()
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp207 constrainOperandRegClass(MF, *TRI, MRI, *STI.getInstrInfo(), in lowerCall()
/aosp_15_r20/external/llvm/include/llvm/CodeGen/
H A DFastISel.h476 unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/CodeGen/
H A DFastISel.h464 Register constrainOperandRegClass(const MCInstrDesc &II, Register Op,

12