Searched +full:xps +full:- +full:uartlite +full:- +full:1 (Results 1 – 6 of 6) sorted by relevance
/linux-6.14.4/Documentation/devicetree/bindings/serial/ |
D | xlnx,opb-uartlite.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/serial/xlnx,opb-uartlite.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Xilinx Axi Uartlite 10 - Peter Korsgaard <[email protected]> 16 - xlnx,xps-uartlite-1.00.a 17 - xlnx,opb-uartlite-1.00.b 20 maxItems: 1 23 maxItems: 1 [all …]
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/linux-6.14.4/Documentation/devicetree/bindings/ |
D | xilinx.txt | 10 Each IP-core has a set of parameters which the FPGA designer can use to 20 properties of the device node. In general, device nodes for IP-cores 23 (name): (generic-name)@(base-address) { 24 compatible = "xlnx,(ip-core-name)-(HW_VER)" 27 interrupt-parent = <&interrupt-controller-phandle>; 29 xlnx,(parameter1) = "(string-value)"; 30 xlnx,(parameter2) = <(int-value)>; 33 (generic-name): an open firmware-style name that describes the 36 (ip-core-name): the name of the ip block (given after the BEGIN 38 and all underscores '_' converted to dashes '-'. [all …]
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/linux-6.14.4/drivers/tty/serial/ |
D | uartlite.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * uartlite.c: Serial driver for Xilinx uartlite serial controller 36 /* --------------------------------------------------------------------- 70 * struct uartlite_data - Driver private data 120 struct uartlite_data *pdata = port->private_data; in uart_in32() 122 return pdata->reg_ops->in(port->membase + offset); in uart_in32() 127 struct uartlite_data *pdata = port->private_data; in uart_out32() 129 pdata->reg_ops->out(val, port->membase + offset); in uart_out32() 136 /* --------------------------------------------------------------------- 142 struct tty_port *tport = &port->state->port; in ulite_receive() [all …]
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/linux-6.14.4/arch/sh/boot/dts/ |
D | j2_mimas_v2.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 5 compatible = "jcore,j2-soc"; 8 #address-cells = <1>; 9 #size-cells = <1>; 11 interrupt-parent = <&aic>; 14 #address-cells = <1>; 15 #size-cells = <0>; 21 clock-frequency = <50000000>; 22 d-cache-size = <8192>; [all …]
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/linux-6.14.4/arch/microblaze/boot/dts/ |
D | system.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 5 * (C) Copyright 2007-2008 Xilinx, Inc. 6 * (C) Copyright 2007-2009 Michal Simek 13 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101 16 /dts-v1/; 18 #address-cells = <1>; 19 #size-cells = <1>; 32 stdout-path = "/plb@0/serial@84000000"; 35 #address-cells = <1>; 37 #size-cells = <0>; [all …]
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/linux-6.14.4/ |
D | MAINTAINERS | 5 --------------------------------------------------- 21 W: *Web-page* with status/info 23 B: URI for where to file *bugs*. A web-page with detailed bug 28 patches to the given subsystem. This is either an in-tree file, 29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst 46 N: [^a-z]tegra all files whose path contains tegra 64 ---------------- 83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS) 85 L: linux-[email protected] 88 F: drivers/scsi/3w-* [all …]
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