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/linux-6.14.4/Documentation/devicetree/bindings/memory-controllers/
Darm,pl172.txt5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
[all …]
Dst,stm32-fmc2-ebi-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <[email protected]>
11 - Marek Vasut <[email protected]>
14 st,fmc2-ebi-cs-transaction-type:
25 8: Synchronous read synchronous write PSRAM.
26 9: Synchronous read asynchronous write PSRAM.
27 10: Synchronous read synchronous write NOR.
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/linux-6.14.4/drivers/net/hamradio/
Dz8530.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Write Register 0 */
37 /* Write Register 1 */
39 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
40 #define TxINT_ENAB 0x2 /* Tx Int Enable */
50 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
52 /* Write Register #2 (Interrupt Vector) */
54 /* Write Register 3 */
56 #define RxENABLE 0x1 /* Rx Enable */
59 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
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/linux-6.14.4/arch/arm/mach-sa1100/include/mach/
DSA-1100.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * FILE SA-1100.h
9 * System StrongARM SA-1100
12 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
14 * StrongARM SA-1100 data sheet version 2.2.
21 #error You must include hardware.h not SA-1100.h
81 * Controller (UDC) Control Register (read/write).
83 * Controller (UDC) Address Register (read/write).
86 * (read/write).
89 * (read/write).
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/linux-6.14.4/drivers/tty/serial/
Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
30 /* Write Register 0 */
61 /* Write Register 1 */
63 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
64 #define TxINT_ENAB 0x2 /* Tx Int Enable */
75 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
77 /* Write Register #2 (Interrupt Vector) */
79 /* Write Register 3 */
81 #define RxENAB 0x1 /* Rx Enable */
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Dzs.h1 /* SPDX-License-Identifier: GPL-2.0 */
34 u8 regs[ZS_NUM_REGS]; /* Channel write registers. */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
59 /* Write Register 0 (Command) */
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
91 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
92 #define TxINT_ENAB 0x2 /* Tx Int Enable */
103 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
105 /* Write Register 2 (Interrupt Vector) */
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Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
38 /* Write Register 0 */
69 /* Write Register 1 */
71 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
72 #define TxINT_ENAB 0x2 /* Tx Int Enable */
83 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
85 /* Write Register #2 (Interrupt Vector) */
87 /* Write Register 3 */
89 #define RxENAB 0x1 /* Rx Enable */
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Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
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/linux-6.14.4/Documentation/ABI/testing/
Dsysfs-driver-xdata1 What: /sys/class/misc/drivers/dw-xdata-pcie.<device>/write
5 Description: Allows the user to enable the PCIe traffic generator which
6 will create write TLPs frames - from the Root Complex to the
10 Write y/1/on to enable, n/0/off to disable
13 echo 1 > /sys/class/misc/dw-xdata-pcie.<device>/write
15 echo 0 > /sys/class/misc/dw-xdata-pcie.<device>/write
21 cat /sys/class/misc/dw-xdata-pcie.<device>/write
24 The file is read and write.
26 What: /sys/class/misc/dw-xdata-pcie.<device>/read
30 Description: Allows the user to enable the PCIe traffic generator which
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/linux-6.14.4/drivers/infiniband/ulp/rtrs/
Drtrs-clt-stats.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2014 - 2018 ProfitBricks GmbH. All rights reserved.
6 * Copyright (c) 2018 - 2019 1&1 IONOS Cloud GmbH. All rights reserved.
7 * Copyright (c) 2019 - 2020 1&1 IONOS SE. All rights reserved.
12 #include "rtrs-clt.h"
16 struct rtrs_clt_path *clt_path = to_clt_path(con->c.path); in rtrs_clt_update_wc_stats()
17 struct rtrs_clt_stats *stats = clt_path->stats; in rtrs_clt_update_wc_stats()
22 s = get_cpu_ptr(stats->pcpu_stats); in rtrs_clt_update_wc_stats()
23 if (con->cpu != cpu) { in rtrs_clt_update_wc_stats()
24 s->cpu_migr.to++; in rtrs_clt_update_wc_stats()
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/linux-6.14.4/include/linux/
Dfsl_ifc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 * - IFC version 1.0 implements 4 banks.
22 * - IFC version 1.1 onward implements 8 banks.
35 * CSPR - Chip Select Property Register
47 /* Write Protect */
69 (__ilog2(n) - IFC_AMASK_SHIFT))
74 /* Enable ECC Encoder */
81 /* Enable ECC Decoder */
110 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
111 /* Time for Read Enable High to Output High Impedance */
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/linux-6.14.4/Documentation/devicetree/bindings/cache/
Dl2c2x0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <[email protected]>
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
35 - arm,l220-cache
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/linux-6.14.4/drivers/media/i2c/adv748x/
Dadv748x-core.c1 // SPDX-License-Identifier: GPL-2.0+
21 #include <linux/v4l2-dv-timings.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-dv-timings.h>
26 #include <media/v4l2-fwnode.h>
27 #include <media/v4l2-ioctl.h>
31 /* -----------------------------------------------------------------------------
63 if (!state->i2c_clients[region]) in adv748x_configure_regmap()
64 return -ENODEV; in adv748x_configure_regmap()
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/linux-6.14.4/arch/m68k/include/asm/
Dm54xxacr.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #define CACR_DEC 0x80000000 /* Enable data cache */
13 #define CACR_DWP 0x40000000 /* Data write protection */
14 #define CACR_DESB 0x20000000 /* Enable data store buffer */
17 #define CACR_DDCM_WT 0x00000000 /* Write through cache*/
22 #define CACR_BEC 0x00080000 /* Enable branch cache */
24 #define CACR_IEC 0x00008000 /* Enable instruction cache */
30 #define CACR_EUSP 0x00000020 /* Enable separate user a7 */
34 #define ACR_ENABLE 0x00008000 /* Enable address */
38 #define ACR_CM_WT 0x00000000 /* Write through mode */
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Dmcfmmu.h2 * mcfmmu.h -- definitions for the ColdFire v4e MMU
35 #define MMUCR_EN 0x00000001 /* Virtual mode enable */
44 #define MMUOR_WR 0x00000000 /* TLB access write */
47 #define MMUOR_CAS 0x00000020 /* Clear non-locked ASID TLBs */
48 #define MMUOR_CNL 0x00000040 /* Clear non-locked TLBs */
58 #define MMUSR_WF 0x00000008 /* Write access fault */
63 * MMU Read/Write Tag register.
73 * MMU Read/Write Data register.
76 #define MMUDR_X 0x00000004 /* Execute access enable */
77 #define MMUDR_W 0x00000008 /* Write access enable */
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/linux-6.14.4/drivers/char/xilinx_hwicap/
Dfifo_icap.c24 * (c) Copyright 2007-2008 Xilinx Inc.
28 * with this program; if not, write to the Free Software Foundation, Inc.,
36 #define XHI_GIER_OFFSET 0x1C /* Device Global Interrupt Enable Reg */
38 #define XHI_IPIER_OFFSET 0x28 /* Interrupt Enable Register */
39 #define XHI_WF_OFFSET 0x100 /* Write FIFO */
44 #define XHI_WFV_OFFSET 0x114 /* Write FIFO Vacancy Register */
47 /* Device Global Interrupt Enable Register (GIER) bit definitions */
49 #define XHI_GIER_GIE_MASK 0x80000000 /* Global Interrupt enable Mask */
52 * HwIcap Device Interrupt Status/Enable Registers
56 * write.
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/linux-6.14.4/drivers/misc/eeprom/
Deeprom_93cx6.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2004 - 2006 rt2x00 SourceForge Project
24 eeprom->reg_data_clock = 1; in eeprom_93cx6_pulse_high()
25 eeprom->register_write(eeprom); in eeprom_93cx6_pulse_high()
37 eeprom->reg_data_clock = 0; in eeprom_93cx6_pulse_low()
38 eeprom->register_write(eeprom); in eeprom_93cx6_pulse_low()
51 * Clear all flags, and enable chip select. in eeprom_93cx6_startup()
53 eeprom->register_read(eeprom); in eeprom_93cx6_startup()
54 eeprom->reg_data_in = 0; in eeprom_93cx6_startup()
55 eeprom->reg_data_out = 0; in eeprom_93cx6_startup()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 Enable this driver to get read/write support to most I2C EEPROMs
15 board. Use these generic chip names, instead of vendor-specific
24 as read-only won't help recover from this. Also, if your chip
25 has any software write-protect mechanism you may want to review the
41 Enable this driver to get read/write support to most SPI EEPROMs
53 If you say yes here you get read-only support for the user EEPROM of
54 the Maxim MAX6874/5 EEPROM-programmable, quad power-supply
57 All other features of this chip should be accessed via i2c-dev.
67 The driver supports both read as well as write commands.
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/linux-6.14.4/drivers/comedi/drivers/
Dplx9080.h1 /* SPDX-License-Identifier: GPL-2.0+ */
26 * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
32 * Describes the format of a scatter-gather DMA descriptor for the PLX
33 * PCI 9080. All members are raw, little-endian register values that
37 * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0
74 #define PLX_LASBA_EN BIT(0) /* Enable slave decode */
93 /* Local Bus Latency Timer Enable */
95 /* Local Bus Pause Timer Enable */
97 /* Local Bus BREQ Enable */
106 /* Direct Slace LLOCKo# Enable */
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/linux-6.14.4/drivers/rtc/
Drtc-imxdi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
8 * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block
10 * Since the RTC framework performs API locking via rtc->ops_lock the
15 * the WCF (Write Complete Flag). All DryIce writes are synchronized to the
17 * DIER (DryIce Interrupt Enable Register) are the only exception. These
41 #define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
44 #define DCR_TDCHL (1 << 30) /* Tamper-detect configuration hard lock */
45 #define DCR_TDCSL (1 << 29) /* Tamper-detect configuration soft lock */
46 #define DCR_KSSL (1 << 27) /* Key-select soft lock */
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/linux-6.14.4/arch/sh/drivers/pci/
Dpci-sh4.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include "pci-sh7780.h"
10 #include "pci-sh7751.h"
16 #define SH4_PCICR_PREFIX 0xA5000000 /* CR prefix for write */
17 #define SH4_PCICR_FTO 0x00000400 /* TRDY/IRDY Enable */
20 #define SH4_PCICR_PLUP 0x00000080 /* Enable PCI Pullup */
38 #define SH4_PCIINT_TWDP 0x00000020 /* Tgt. Write Parity Error */
40 #define SH4_PCIINT_MTABT 0x00000008 /* Master-Tgt. Abort Error */
41 #define SH4_PCIINT_MMABT 0x00000004 /* Master-Master Abort Error */
42 #define SH4_PCIINT_MWPD 0x00000002 /* Master Write PERR Detect */
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/linux-6.14.4/drivers/leds/
Dleds-is31fl32xx.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * http://www.issi.com/US/product-analog-fxled-driver.shtml
9 * http://www.si-en.com/product.asp?parentid=890
38 u8 channel; /* 1-based, max priv->cdef->channels */
50 * struct is31fl32xx_chipdef - chip-specific attributes
59 * @enable_bits_per_led_control_register: number of LEDs enable bits in each
66 * If non-NULL, @reset_func will be called during probing to set all
84 int (*sw_shutdown_func)(struct is31fl32xx_priv *priv, bool enable);
122 bool enable);
141 dev_dbg(&priv->client->dev, "writing register 0x%02X=0x%02X", reg, val); in is31fl32xx_write()
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/linux-6.14.4/drivers/mtd/nand/raw/
Dr852.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2009 - Maxim Levitsky
15 byte write/read does one cycle on nand data lines.
16 dword write/read does 4 cycles
19 If write was done two dword reads read generated ecc checksums
26 #define R852_CTL_DATA 0x02 /* read/write data (#ALE)*/
30 #define R852_CTL_CARDENABLE 0x10 /* probably (#CE) - always set*/
31 #define R852_CTL_ECC_ENABLE 0x20 /* enable ecc engine */
32 #define R852_CTL_ECC_ACCESS 0x40 /* read/write ecc via reg #0*/
42 #define R852_CARD_STA_BUSY 0x80 /* card is busy - (#R/B) */
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/linux-6.14.4/drivers/net/ethernet/freescale/fman/
Dfman_keygen.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
36 /* Enable bit field mask for KeyGen General Configuration Register */
96 /* Hard-coded configuration:
97 * These values are used as hard-coded values for KeyGen configuration
98 * and they replace user selections for this hard-coded version
109 * - the value for symmetric hash usage must be in accordance with hash
111 * - according to tests performed, spreading is not working if symmetric
173 u32 fmkg_eeer; /* 0x010: KeyGen Error Event Enable Register */
177 u32 fmkg_seeer; /* 0x020: KeyGen Scheme Error Event Enable Register */
207 * Must be between 1 and 2^24-1
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/linux-6.14.4/drivers/net/ethernet/aquantia/atlantic/hw_atl/
Dhw_atl_llh.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
140 /* set interrupt mapping enable rx */
144 /* set interrupt mapping enable tx */
178 void hw_atl_itr_rsc_en_set(struct aq_hw_s *aq_hw, u32 enable);
188 /* set rx dca enable */
199 /* set rx descriptor dca enable */
203 /* set rx descriptor enable */
219 /* set rx descriptor write-back interrupt enable */
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