Lines Matching +full:write +full:- +full:enable
1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <[email protected]>
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
35 - arm,l220-cache
36 - arm,l210-cache
37 # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
38 - bcm,bcm11351-a2-pl310-cache
42 - brcm,bcm11351-a2-pl310-cache
47 - marvell,aurora-system-cache
50 - marvell,aurora-outer-cache
51 - items:
53 # with arm,pl310-cache controller.
54 - const: marvell,tauros3-cache
55 - const: arm,pl310-cache
57 cache-level:
60 cache-unified: true
61 cache-size: true
62 cache-sets: true
63 cache-block-size: true
64 cache-line-size: true
69 arm,data-latency:
71 read, write and setup latencies. Minimum valid values are 1. Controllers
73 $ref: /schemas/types.yaml#/definitions/uint32-array
80 arm,tag-latency:
82 read, write and setup latencies. Controllers without setup latency control
83 should use 0. Controllers without separate read and write Tag RAM latency
85 $ref: /schemas/types.yaml#/definitions/uint32-array
92 arm,dirty-latency:
98 arm,filter-ranges:
102 $ref: /schemas/types.yaml#/definitions/uint32-array
106 arm,io-coherent:
108 I/O coherent mode. Valid only when the arm,pl310-cache compatible
117 cache-id-part:
122 wt-override:
123 description: If present then L2 is forced to Write through mode
126 arm,double-linefill:
127 description: Override double linefill enable setting. Enable if
128 non-zero, disable if zero.
132 arm,double-linefill-incr:
133 description: Override double linefill on INCR read. Enable
134 if non-zero, disable if zero.
138 arm,double-linefill-wrap:
139 description: Override double linefill on WRAP read. Enable
140 if non-zero, disable if zero.
144 arm,prefetch-drop:
145 description: Override prefetch drop enable setting. Enable if non-zero,
150 arm,prefetch-offset:
155 arm,shared-override:
158 memory non-cacheable transactions" into "cacheable no allocate" (for reads)
159 or "write through no write allocate" (for writes).
164 arm,parity-enable:
165 description: enable parity checking on the L2 cache (L220 or PL310).
168 arm,parity-disable:
172 marvell,ecc-enable:
173 description: enable ECC protection on the L2 cache
176 arm,outer-sync-disable:
182 prefetch-data:
185 (forcibly enable), property absent (retain settings set by firmware)
189 prefetch-instr:
192 <1> (forcibly enable), property absent (retain settings set by
197 arm,dynamic-clock-gating:
200 disable), <1> (forcibly enable), property absent (OS specific behavior,
205 arm,standby-mode:
206 description: L2 standby mode enable. Value <0> (forcibly disable),
207 <1> (forcibly enable), property absent (OS specific behavior,
212 arm,early-bresp-disable:
216 arm,full-line-zero-disable:
218 write (PL310)
222 - compatible
223 - cache-unified
224 - reg
229 - |
230 cache-controller@fff12000 {
231 compatible = "arm,pl310-cache";
233 arm,data-latency = <1 1 1>;
234 arm,tag-latency = <2 2 2>;
235 arm,filter-ranges = <0x80000000 0x8000000>;
236 cache-unified;
237 cache-level = <2>;