Searched full:vlenb (Results 1 – 9 of 9) sorted by relevance
| /linux-6.14.4/arch/riscv/kvm/ |
| D | vcpu_vector.c | 79 cntx->vector.vlenb = riscv_v_vsize / 32; in kvm_riscv_vcpu_alloc_vector_context()
101 size_t vlenb = riscv_v_vsize / 32; in kvm_riscv_vcpu_vreg_addr() local
119 case KVM_REG_RISCV_VECTOR_CSR_REG(vlenb): in kvm_riscv_vcpu_vreg_addr()
120 *reg_addr = &cntx->vector.vlenb; in kvm_riscv_vcpu_vreg_addr()
127 if (reg_size != vlenb) in kvm_riscv_vcpu_vreg_addr()
130 (reg_num - KVM_REG_RISCV_VECTOR_REG(0)) * vlenb; in kvm_riscv_vcpu_vreg_addr()
180 if (reg_num == KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)) { in kvm_riscv_vcpu_set_reg_vector()
186 if (reg_val != cntx->vector.vlenb) in kvm_riscv_vcpu_set_reg_vector()
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| D | vcpu_onereg.c | 1104 /* vstart, vl, vtype, vcsr, vlenb and 32 vector regs */ in num_vector_regs()
1119 /* copy vstart, vl, vtype, vcsr and vlenb */ in copy_vector_reg_indices()
1131 /* vector_regs have a variable 'vlenb' size */ in copy_vector_reg_indices()
1132 size = __builtin_ctzl(cntx->vector.vlenb); in copy_vector_reg_indices()
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| /linux-6.14.4/arch/riscv/include/uapi/asm/ |
| D | ptrace.h | 105 unsigned long vlenb; member
119 unsigned long vlenb; member
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| /linux-6.14.4/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 40 thead,vlenb: false
111 thead,vlenb:
116 the vlenb CSR is not available.
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| /linux-6.14.4/arch/riscv/kernel/ |
| D | ptrace.c | 115 ptrace_vstate.vlenb = vstate->vlenb; in riscv_vr_get()
142 if (vstate->vlenb != ptrace_vstate.vlenb) in riscv_vr_set()
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| D | vector.c | 37 * There are 32 vector registers with vlenb length. in riscv_v_setup_vsize()
39 * If the thead,vlenb property was provided by the firmware, use that in riscv_v_setup_vsize()
57 WARN(1, "RISCV_ISA_V only supports one vlenb on SMP systems"); in riscv_v_setup_vsize()
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| D | cpufeature.c | 802 u32 vlenb; in has_thead_homogeneous_vlenb() local
804 /* Ignore thead,vlenb property if xtheavector is not enabled in the kernel */ in has_thead_homogeneous_vlenb()
817 if (of_property_read_u32(cpu_node, "thead,vlenb", &vlenb)) { in has_thead_homogeneous_vlenb()
825 if (prev_vlenb && vlenb != prev_vlenb) { in has_thead_homogeneous_vlenb()
830 prev_vlenb = vlenb; in has_thead_homogeneous_vlenb()
834 thead_vlenb_of = vlenb; in has_thead_homogeneous_vlenb()
899 pr_warn("Unsupported heterogeneous vlenb detected, vector extension disabled.\n"); in riscv_fill_hwcap_from_ext_list()
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| /linux-6.14.4/arch/riscv/include/asm/ |
| D | vector.h | 151 dest->vlenb = riscv_v_vsize / 32; in __vstate_csr_save()
157 dest->vlenb = csr_read(CSR_VLENB); in __vstate_csr_save()
416 * riscv_v_vsize contains the value of "32 vector registers with vlenb length"
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| /linux-6.14.4/arch/riscv/boot/dts/allwinner/ |
| D | sun20i-d1s.dtsi | 31 thead,vlenb = <128>;
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