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/linux-6.14.4/Documentation/devicetree/bindings/firmware/xilinx/
Dxlnx,zynqmp-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx firmware driver
10 - Nava kishore Manne <[email protected]>
12 description: The zynqmp-firmware node describes the interface to platform
13 firmware. ZynqMP has an interface to communicate with secure firmware.
14 Firmware driver provides an interface to firmware APIs. Interface APIs
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
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/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dxlnx,versal-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal clock controller
10 - Michal Simek <[email protected]>
13 The clock controller is a hardware block of Xilinx versal clock tree. It
20 - enum:
21 - xlnx,versal-clk
22 - xlnx,zynqmp-clk
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/linux-6.14.4/Documentation/devicetree/bindings/fpga/
Dxlnx,versal-fpga.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal FPGA driver.
10 - Nava kishore Manne <[email protected]>
13 Device Tree Versal FPGA bindings for the Versal SoC, controlled
14 using firmware interface.
19 - enum:
20 - xlnx,versal-fpga
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/linux-6.14.4/drivers/fpga/
Dversal-fpga.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2021 Xilinx, Inc.
6 #include <linux/dma-mapping.h>
7 #include <linux/fpga/fpga-mgr.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
29 kbuf = dma_alloc_coherent(mgr->dev.parent, size, &dma_addr, GFP_KERNEL); in versal_fpga_ops_write()
31 return -ENOMEM; in versal_fpga_ops_write()
35 dma_free_coherent(mgr->dev.parent, size, kbuf, dma_addr); in versal_fpga_ops_write()
47 struct device *dev = &pdev->dev; in versal_fpga_probe()
51 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); in versal_fpga_probe()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
52 FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
100 tristate "Technologic Systems TS-73xx SBC FPGA Manager"
104 present on the TS-73xx SBC boards.
140 safely handles AXI4MM and AXI4-Lite interfaces on a
173 Select this option to enable common support for Field-Programmable
222 the card. It also instantiates the SPI master (spi-altera) for
229 Select this option to enable PCIe driver for PCIe-based
230 Field-Programmable Gate Array (FPGA) solutions which implement
250 tristate "Xilinx Versal FPGA"
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/linux-6.14.4/Documentation/devicetree/bindings/bus/
Dxlnx,versal-net-cdx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/xlnx,versal-net-cdx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 detect CDX bus and devices using the firmware.
15 on run-time.
20 are used to configure SMMU and GIC-ITS respectively.
22 iommu-map property is used to define the set of stream ids
26 The msi-map property is used to associate the devices with the
34 - Nipun Gupta <[email protected]>
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/linux-6.14.4/Documentation/devicetree/bindings/remoteproc/
Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <[email protected]>
11 - Tanmay Shah <[email protected]>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
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/linux-6.14.4/Documentation/devicetree/bindings/mailbox/
Dxlnx,zynqmp-ipi-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 +-------------------------------------+
16 +-------------------------------------+
17 +--------------------------------------------------+
18 TF-A | |
21 +--------------------------+ |
24 +--------------------------------------------------+
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/linux-6.14.4/drivers/reset/
Dreset-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/reset-controller.h>
11 #include <linux/firmware/xlnx-zynqmp.h>
13 #define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START)
39 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_assert()
48 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_deassert()
59 err = zynqmp_pm_reset_get_status(priv->data->reset_id + id, &val); in zynqmp_reset_status()
71 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_reset()
78 return reset_spec->args[0]; in zynqmp_reset_of_xlate()
107 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in zynqmp_reset_probe()
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/linux-6.14.4/Documentation/accel/amdxdna/
Damdnpu.rst1 .. SPDX-License-Identifier: GPL-2.0-only
15 AMD NPU (Neural Processing Unit) is a multi-user AI inference accelerator
27 --------------
44 ----------------
52 ---------------
54 A microcontroller runs NPU Firmware which is responsible for command processing,
58 NPU Firmware uses a dedicated instance of an isolated non-privileged context
62 NPU Firmware uses a single isolated privileged context called MERT to service
66 ---------
79 -------
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/linux-6.14.4/drivers/edac/
DKconfig16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-[email protected].
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
65 When this option is enabled, it will disable the hardware-driven
67 "Firmware First" mode.
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Dversal_edac.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx Versal memory controller driver
15 #include <linux/firmware/xlnx-zynqmp.h>
16 #include <linux/firmware/xlnx-event-manager.h>
133 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/PCSR_LOCK-XRAM_SLCR-Register
149 * struct ecc_error_info - ECC error log information.
195 * struct ecc_status - ECC status information to report.
209 * struct edac_priv - DDR memory controller private instance data.
255 ddrmc_base = priv->ddrmc_baseaddr; in get_ce_error_info()
256 p = &priv->stat; in get_ce_error_info()
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/linux-6.14.4/drivers/cdx/controller/
Dmc_cdx_pcol.h1 /* SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
22 * | | \--- Response
23 * | \------- Error
24 * \------------------------------ Resync (always set)
76 * - To advance a shared memory request if XFLAGS_EVREQ was set
77 * - As a notification (link state, i2c event), controlled
89 * - LEVEL==INFO Command succeeded
90 * - LEVEL==ERR Command failed
101 * non-existent MCDI command MC_CMD_DEBUG_LOG.
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/linux-6.14.4/drivers/remoteproc/
Dxlnx_r5_remoteproc.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/power/xlnx-zynqmp-power.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/firmware/xlnx-zynqmp.h>
12 #include <linux/mailbox/zynqmp-ipi-message.h>
34 * reflects possible values of xlnx,cluster-mode dt-property
38 LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk */
43 * struct mem_bank_data - Memory Bank description
48 * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off
60 * struct zynqmp_sram_bank - sram bank description
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/linux-6.14.4/drivers/clk/zynqmp/
Dclkc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Xilinx
12 #include <linux/clk-provider.h>
19 #include "clk-zynqmp.h"
49 * struct clock_parent - Clock parent
61 * struct zynqmp_clock - Clock
141 * zynqmp_is_valid_clock() - Check whether clock is valid or not
149 return -ENODEV; in zynqmp_is_valid_clock()
155 * zynqmp_get_clock_name() - Get name of clock from Clock index
171 return ret == 0 ? -EINVAL : ret; in zynqmp_get_clock_name()
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/linux-6.14.4/drivers/usb/dwc3/
Ddwc3-xilinx.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver
15 #include <linux/dma-mapping.h>
22 #include <linux/firmware/xlnx-zynqmp.h>
59 reg = readl(priv_data->regs + XLNX_USB_PHY_RST_EN); in dwc3_xlnx_mask_phy_rst()
66 writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN); in dwc3_xlnx_mask_phy_rst()
71 struct device *dev = priv_data->dev; in dwc3_xlnx_init_versal()
81 /* Assert and De-assert reset */ in dwc3_xlnx_init_versal()
90 dev_err_probe(dev, ret, "failed to De-assert Reset\n"); in dwc3_xlnx_init_versal()
101 struct device *dev = priv_data->dev; in dwc3_xlnx_init_zynqmp()
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/linux-6.14.4/drivers/pinctrl/
Dpinctrl-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 #include <linux/firmware/xlnx-zynqmp.h>
22 #include <linux/pinctrl/pinconf-generic.h>
28 #include "pinctrl-utils.h"
55 * struct zynqmp_pmux_function - a pinmux function
70 * struct zynqmp_pinctrl - driver data
90 * struct zynqmp_pctrl_group - Pin control group info
109 return pctrl->ngroups + zynqmp_desc.npins; in zynqmp_pctrl_get_groups_count()
117 if (selector < pctrl->ngroups) in zynqmp_pctrl_get_group_name()
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/linux-6.14.4/drivers/mmc/host/
Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <[email protected]>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
26 #include <linux/firmware/xlnx-zynqmp.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
94 * On some SoCs the syscon area has a feature where the upper 16-bits of
95 * each 32-bit register act as a write mask for the lower 16-bits. This allows
103 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
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/linux-6.14.4/drivers/spi/
Dspi-zynqmp-gqspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
6 * Copyright (C) 2009 - 2015 Xilinx, Inc.
11 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
23 #include <linux/spi/spi-mem.h>
120 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
149 /* set to differentiate versal from zynqmp, 1=versal, 0=zynqmp */
161 * struct qspi_platform_data - zynqmp qspi platform data structure
169 * struct zynqmp_qspi - Defines qspi driver instance
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Dspi-cadence-quadspi.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
16 #include <linux/firmware/xlnx-zynqmp.h>
30 #include <linux/spi/spi-mem.h>
33 #define CQSPI_NAME "cadence-qspi"
321 if (ret != -ETIMEDOUT) in cqspi_wait_for_bit()
324 timeout_us -= CQSPI_BUSYWAIT_TIMEOUT_US; in cqspi_wait_for_bit()
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/linux-6.14.4/drivers/cdx/
Dcdx.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
13 * Firmware and the APUs (Application CPUs).
15 * Firmware resides on RPU (Realtime CPUs) which interacts with
16 * the FPGA program manager and the APUs. The RPU provides memory-mapped
21 * +--------------------------------------+
30 * +-----------------------------|--------+
34 * +------------------------| RPU if |----+
39 * +--------------------------------------+
41 * +---------------------|----------------+
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/linux-6.14.4/drivers/firmware/xilinx/
Dzynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx Zynq MPSoC Firmware layer
5 * Copyright (C) 2014-2022 Xilinx, Inc.
6 * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
14 #include <linux/arm-smccc.h>
27 #include <linux/firmware/xlnx-zynqmp.h>
28 #include <linux/firmware/xlnx-event-manager.h>
29 #include "zynqmp-debug.h"
36 /* BOOT_PIN_CTRL- Used to control the mode pins after boot */
38 /* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */
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/linux-6.14.4/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-[email protected]
88 F: drivers/scsi/3w-*
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/linux-6.14.4/drivers/net/ethernet/cadence/
Dmacb_main.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2006 Atmel Corporation
10 #include <linux/clk-provider.h>
25 #include <linux/dma-mapping.h>
40 #include <linux/firmware/xlnx-zynqmp.h>
58 * (bp)->rx_ring_size)
64 * (bp)->tx_ring_size)
67 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
78 …MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN -…
94 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
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