| /linux-6.14.4/sound/soc/intel/common/ |
| D | soc-acpi-intel-tgl-match.c | 3 * soc-acpi-intel-tgl-match.c - tables and support for TGL ACPI enumeration.
512 .sof_tplg_filename = "sof-tgl-es8336", /* the tplg suffix is added at run time */
523 .sof_tplg_filename = "sof-tgl", /* the tplg suffix is added at run time */
533 .sof_tplg_filename = "sof-tgl-rt1308-ssp2-hdmi-ssp15.tplg"
734 .sof_tplg_filename = "sof-tgl-rt711-rt1308-rt715.tplg",
740 .sof_tplg_filename = "sof-tgl-rt711-rt1308-mono-rt715.tplg",
746 .sof_tplg_filename = "sof-tgl-rt715-rt711-rt1308-mono.tplg",
752 .sof_tplg_filename = "sof-tgl-rt712.tplg",
758 .sof_tplg_filename = "sof-tgl-rt715-rt711-rt1308-mono.tplg",
764 .sof_tplg_filename = "sof-tgl-cs42l43-l3-cs35l56-l01.tplg",
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| D | Makefile | 8 soc-acpi-intel-tgl-match.o soc-acpi-intel-ehl-match.o \
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| /linux-6.14.4/sound/soc/sof/intel/ |
| D | pci-tgl.c | 36 [SOF_IPC_TYPE_4] = "intel/sof-ipc4/tgl",
39 [SOF_IPC_TYPE_4] = "intel/sof-ipc4-lib/tgl",
46 [SOF_IPC_TYPE_3] = "sof-tgl.ri",
47 [SOF_IPC_TYPE_4] = "sof-tgl.ri",
49 .nocodec_tplg_filename = "sof-tgl-nocodec.tplg",
69 [SOF_IPC_TYPE_4] = "intel/sof-ipc4/tgl-h",
72 [SOF_IPC_TYPE_4] = "intel/sof-ipc4-lib/tgl-h",
79 [SOF_IPC_TYPE_3] = "sof-tgl-h.ri",
80 [SOF_IPC_TYPE_4] = "sof-tgl-h.ri",
82 .nocodec_tplg_filename = "sof-tgl-nocodec.tplg",
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| D | Makefile | 34 snd-sof-pci-intel-tgl-y := pci-tgl.o tgl.o
44 obj-$(CONFIG_SND_SOC_SOF_INTEL_TGL) += snd-sof-pci-intel-tgl.o
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| /linux-6.14.4/drivers/gpu/drm/i915/display/ |
| D | intel_dpll_mgr.h | 113 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
117 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
125 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
130 * TGL TC PLL 1 port 1 (TC1)
135 * TGL TC PLL 1 port 2 (TC2)
140 * TGL TC PLL 1 port 3 (TC3)
145 * TGL TC PLL 1 port 4 (TC4)
149 * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5)
153 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
215 /* tgl */
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| D | skl_watermark_regs.h | 15 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20) /* tgl+ */
17 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17) /* tgl+ */
19 #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */
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| D | skl_universal_plane_regs.h | 81 #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
91 #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
353 #define _PLANE_CHICKEN_1_A 0x7026c /* tgl+ */
397 /* tgl+ */
413 /* tgl+ */
428 /* tgl+ */
443 /* tgl+ */
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| D | intel_display_limits.h | 105 /* tgl+ */
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| D | intel_psr_regs.h | 62 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
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| D | intel_cursor_regs.h | 107 /* tgl+ */
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| /linux-6.14.4/arch/powerpc/platforms/powernv/ |
| D | pci-ioda-tce.c | 375 struct iommu_table_group_link *tgl; in pnv_pci_unlink_table_and_group() local
384 list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { in pnv_pci_unlink_table_and_group()
385 if (tgl->table_group == table_group) { in pnv_pci_unlink_table_and_group()
386 list_del_rcu(&tgl->next); in pnv_pci_unlink_table_and_group()
387 kfree_rcu(tgl, rcu); in pnv_pci_unlink_table_and_group()
414 struct iommu_table_group_link *tgl = NULL; in pnv_pci_link_table_and_group() local
419 tgl = kzalloc_node(sizeof(struct iommu_table_group_link), GFP_KERNEL, in pnv_pci_link_table_and_group()
421 if (!tgl) in pnv_pci_link_table_and_group()
424 tgl->table_group = table_group; in pnv_pci_link_table_and_group()
425 list_add_rcu(&tgl->next, &tbl->it_group_list); in pnv_pci_link_table_and_group()
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| /linux-6.14.4/drivers/media/rc/img-ir/ |
| D | img-ir-rc5.c | 14 unsigned int addr, cmd, tgl, start; in img_ir_rc5_scancode() local
20 tgl = (raw >> 11) & 0x01; in img_ir_rc5_scancode()
34 request->toggle = tgl; in img_ir_rc5_scancode()
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| /linux-6.14.4/arch/x86/events/intel/ |
| D | cstate.c | 55 * TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
61 * ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL
66 * KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,
72 * GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL,
79 * TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
85 * KBL,CML,ICL,TGL,RKL
89 * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL,
94 * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL
98 * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,
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| /linux-6.14.4/drivers/gpu/drm/i915/gt/ |
| D | intel_workarounds.c | 694 * Wa_1409142259:tgl,dg1,adl-p in gen12_ctx_workarounds_init()
695 * Wa_1409347922:tgl,dg1,adl-p in gen12_ctx_workarounds_init()
696 * Wa_1409252684:tgl,dg1,adl-p in gen12_ctx_workarounds_init()
697 * Wa_1409217633:tgl,dg1,adl-p in gen12_ctx_workarounds_init()
698 * Wa_1409207793:tgl,dg1,adl-p in gen12_ctx_workarounds_init()
699 * Wa_1409178076:tgl,dg1,adl-p in gen12_ctx_workarounds_init()
700 * Wa_1408979724:tgl,dg1,adl-p in gen12_ctx_workarounds_init()
701 * Wa_14010443199:tgl,rkl,dg1,adl-p in gen12_ctx_workarounds_init()
702 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p in gen12_ctx_workarounds_init()
703 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p in gen12_ctx_workarounds_init()
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| D | intel_mocs.c | 109 * PTE and those platforms except TGL/RKL will be initialized L3 WB to
122 * NOTE2: For GEN >= 12 except TGL and RKL, reserved and unspecified MOCS
126 * For TGL/RKL, all the unspecified MOCS indexes are mapped to L3 UC.
481 /* For TGL/RKL, Can't be changed now for ABI reasons */ in get_mocs_settings()
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| D | intel_tlb.c | 85 /* Wa_2207587034:tgl,dg1,rkl,adl-s,adl-p */ in mmio_invalidate_full()
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| /linux-6.14.4/drivers/gpu/drm/xe/ |
| D | xe_uc_fw.c | 115 fw_def(ALDERLAKE_N, major_ver(i915, guc, tgl, 70, 29, 2)) \
117 fw_def(ALDERLAKE_S, major_ver(i915, guc, tgl, 70, 29, 2)) \
118 fw_def(ROCKETLAKE, major_ver(i915, guc, tgl, 70, 29, 2)) \
119 fw_def(TIGERLAKE, major_ver(i915, guc, tgl, 70, 29, 2))
126 fw_def(ALDERLAKE_P, no_ver(i915, huc, tgl)) \
127 fw_def(ALDERLAKE_S, no_ver(i915, huc, tgl)) \
128 fw_def(ROCKETLAKE, no_ver(i915, huc, tgl)) \
129 fw_def(TIGERLAKE, no_ver(i915, huc, tgl))
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| /linux-6.14.4/drivers/gpu/drm/i915/gt/uc/ |
| D | intel_uc_fw.c | 69 * firmware as TGL.
96 fw_def(ALDERLAKE_S, 0, guc_maj(tgl, 70, 12, 1)) \
97 fw_def(ALDERLAKE_S, 0, guc_mmp(tgl, 70, 1, 1)) \
98 fw_def(ALDERLAKE_S, 0, guc_mmp(tgl, 69, 0, 3)) \
100 fw_def(ROCKETLAKE, 0, guc_mmp(tgl, 70, 1, 1)) \
101 fw_def(TIGERLAKE, 0, guc_mmp(tgl, 70, 1, 1)) \
116 fw_def(ALDERLAKE_P, 0, huc_raw(tgl)) \
117 fw_def(ALDERLAKE_P, 0, huc_mmp(tgl, 7, 9, 3)) \
118 fw_def(ALDERLAKE_S, 0, huc_raw(tgl)) \
119 fw_def(ALDERLAKE_S, 0, huc_mmp(tgl, 7, 9, 3)) \
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| /linux-6.14.4/drivers/platform/x86/intel/pmc/ |
| D | Makefile | 7 icl.o tgl.o adl.o mtl.o arl.o lnl.o
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| /linux-6.14.4/drivers/gpu/drm/imx/dcss/ |
| D | dcss-dev.h | 17 #define TGL 0x0C macro
23 #define dcss_toggle(v, c) writel((v), (c) + TGL)
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| /linux-6.14.4/Documentation/gpu/xe/ |
| D | index.rst | 8 compute and media. Support for currently available platforms like TGL, ADL,
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| /linux-6.14.4/sound/soc/intel/avs/ |
| D | Makefile | 7 snd-soc-avs-y += skl.o apl.o cnl.o icl.o tgl.o
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| /linux-6.14.4/drivers/gpu/drm/ci/ |
| D | test.yml | 296 i915:tgl:
302 GPU_VERSION: tgl
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| /linux-6.14.4/drivers/soundwire/ |
| D | dmi-quirks.c | 94 /* TGL devices */
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| /linux-6.14.4/drivers/gpu/drm/i915/ |
| D | i915_reg.h | 1656 #define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
1681 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */
1937 #define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
1957 #define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
1965 #define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */
2211 #define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */
2212 #define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl+ */
2214 #define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */
2215 #define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */
2217 #define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */
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