Lines Matching full:tgl
1656 #define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
1681 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */
1937 #define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
1957 #define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
1965 #define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */
2211 #define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */
2212 #define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl+ */
2214 #define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */
2215 #define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */
2217 #define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */
2219 #define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */
2220 #define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */
2222 #define GEN12_DSB_2_INT REG_BIT(15) /* tgl+ */
2223 #define GEN12_DSB_1_INT REG_BIT(14) /* tgl+ */
2224 #define GEN12_DSB_0_INT REG_BIT(13) /* tgl+ */
2523 #define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */
3410 /* ICL/TGL - power wells */
4186 /* tgl+ */