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/linux-6.14.4/Documentation/devicetree/bindings/ptp/
Dfsl,ptp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <[email protected]>
15 - enum:
16 - fsl,etsec-ptp
17 - fsl,fman-ptp-timer
18 - fsl,dpaa2-ptp
19 - items:
20 - const: pci1957,ee02
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/linux-6.14.4/Documentation/devicetree/bindings/watchdog/
Dsnps,dw-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/watchdog/snps,dw-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jamie Iles <[email protected]>
13 - $ref: watchdog.yaml#
18 - const: snps,dw-wdt
19 - items:
20 - enum:
21 - rockchip,px30-wdt
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/linux-6.14.4/arch/powerpc/boot/dts/fsl/
Dbsc9131rdb.dtsi2 * BSC9131 RDB Device Tree Source stub (no addresses or top-level ranges)
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
38 #address-cells = <1>;
39 #size-cells = <1>;
40 compatible = "fsl,ifc-nand";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 compatible = "spansion,s25sl12801", "jedec,spi-nor";
58 spi-max-frequency = <50000000>;
68 phy0: ethernet-phy@0 {
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Dbsc9132qds.dtsi2 * BSC9132 QDS Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,ifc-nand";
56 #address-cells = <1>;
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Dp1022ds.dtsi2 * P1022 DS Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 label = "ramdisk-nor";
47 read-only;
52 label = "diagnostic-nor";
53 read-only;
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Dp1010rdb.dtsi2 * P1010 RDB Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
64 /* 512KB for u-boot Bootloader Image */
65 /* 512KB for u-boot Environment Variables */
67 label = "NOR U-Boot Image";
68 read-only;
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Dp2020rdb-pc.dtsi2 * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
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Dp2020rdb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2009-2012 Freescale Semiconductor Inc.
8 /include/ "p2020si-pre.dtsi"
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR (RO) Vitesse-7385 Firmware";
49 read-only;
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Dp1021rdb-pc.dtsi2 * P1021 RDB Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
75 read-only;
80 /* 512KB for u-boot Bootloader Image */
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Dp1020rdb-pd.dts2 * P1020 RDB-PD Device Tree Source (32-bit address map)
35 /include/ "p1020si-pre.dtsi"
37 model = "fsl,P1020RDB-PD";
38 compatible = "fsl,P1020RDB-PD";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 compatible = "cfi-flash";
58 bank-width = <2>;
59 device-width = <1>;
83 label = "NOR Vitesse-7385 Firmware";
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Dp2020ds.dtsi2 * P2020DS Device Tree Source stub (no addresses or top-level ranges)
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 read-only;
51 read-only;
56 read-only;
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Dp1025twr.dtsi2 * P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "cfi-flash";
48 bank-width = <2>;
49 device-width = <1>;
55 label = "NOR Vitesse-7385 Firmware";
56 read-only;
82 read-only;
87 /* 512KB for u-boot Bootloader Image */
[all …]
Dmpc8572ds.dtsi2 * MPC8572DS Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 label = "ramdisk-nor";
51 label = "diagnostic-nor";
52 read-only;
57 label = "dink-nor";
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/linux-6.14.4/drivers/i2c/busses/
Di2c-octeon-core.c2 * (C) Copyright 2009-2010
5 * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
22 #include "i2c-octeon-core.h"
33 i2c->int_disable(i2c); in octeon_i2c_isr()
34 wake_up(&i2c->queue); in octeon_i2c_isr()
45 * octeon_i2c_wait - wait for the IFLG to be set
58 if (i2c->broken_irq_mode) { in octeon_i2c_wait()
59 u64 end = get_jiffies_64() + i2c->adap.timeout; in octeon_i2c_wait()
65 return octeon_i2c_test_iflg(i2c) ? 0 : -ETIMEDOUT; in octeon_i2c_wait()
68 i2c->int_enable(i2c); in octeon_i2c_wait()
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/linux-6.14.4/drivers/media/platform/ti/omap3isp/
Dispcsiphy.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - CSI PHY module
30 regmap_read(phy->isp->syscon, phy->isp->syscon_offset, &reg); in csiphy_routing_cfg_3630()
66 regmap_write(phy->isp->syscon, phy->isp->syscon_offset, reg); in csiphy_routing_cfg_3630()
80 regmap_write(phy->isp->syscon, phy->isp->syscon_offset, 0); in csiphy_routing_cfg_3430()
87 regmap_write(phy->isp->syscon, phy->isp->syscon_offset, csirxfe); in csiphy_routing_cfg_3430()
99 * and 3630, so they will not hold their contents in off-mode. This isn't an
106 if (phy->isp->phy_type == ISP_PHY_TYPE_3630 && on) in csiphy_routing_cfg()
108 if (phy->isp->phy_type == ISP_PHY_TYPE_3430) in csiphy_routing_cfg()
118 isp_reg_clr_set(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG, in csiphy_power_autoswitch_enable()
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/linux-6.14.4/drivers/ptp/
Dptp_qoriq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
26 /* Caller must hold ptp_qoriq->lock. */
29 struct ptp_qoriq_registers *regs = &ptp_qoriq->regs; in tmr_cnt_read()
33 lo = ptp_qoriq->read(&regs->ctrl_regs->tmr_cnt_l); in tmr_cnt_read()
34 hi = ptp_qoriq->read(&regs->ctrl_regs->tmr_cnt_h); in tmr_cnt_read()
40 /* Caller must hold ptp_qoriq->lock. */
43 struct ptp_qoriq_registers *regs = &ptp_qoriq->regs; in tmr_cnt_write()
47 ptp_qoriq->write(&regs->ctrl_regs->tmr_cnt_l, lo); in tmr_cnt_write()
48 ptp_qoriq->write(&regs->ctrl_regs->tmr_cnt_h, hi); in tmr_cnt_write()
53 struct ptp_qoriq_registers *regs = &ptp_qoriq->regs; in tmr_offset_read()
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/linux-6.14.4/drivers/net/wireless/ath/ath9k/
Dhw.h2 * Copyright (c) 2008-2011 Atheros Communications Inc.
70 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
72 #define ATH_DEFAULT_NOISE_FLOOR -95
74 #define ATH9K_RSSI_BAD -128
80 (_ah)->reg_ops.write((_ah), (_val), (_reg))
83 (_ah)->reg_ops.read((_ah), (_reg))
86 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
89 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
93 if ((_ah)->reg_ops.enable_write_buffer) \
94 (_ah)->reg_ops.enable_write_buffer((_ah)); \
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/linux-6.14.4/drivers/pwm/
Dpwm-samsung.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Ben Dooks <[email protected]>, <ben-[email protected]>
59 * struct samsung_pwm_channel - private data of PWM channel
60 * @period_ns: current period in nanoseconds programmed to the hardware
71 * struct samsung_pwm_chip - private data of PWM chip
73 * @inverter_mask: inverter status for all channels - one bit per channel
74 * @disabled_mask: disabled status for all channels - one bit per channel
95 * PWM block is shared between pwm-samsung and samsung_pwm_timer drivers
123 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); in __pwm_samsung_manual_update()
126 tcon = readl(our_chip->base + REG_TCON); in __pwm_samsung_manual_update()
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/linux-6.14.4/arch/powerpc/boot/dts/
Dmpc8313erdb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <32>;
32 i-cache-line-size = <32>;
33 d-cache-size = <16384>;
34 i-cache-size = <16384>;
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Dturris1x.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2013 - 2022 CZ.NIC z.s.p.o. (http://www.nic.cz/)
8 * and available at: https://docs.turris.cz/hw/turris-1x/turris-1x/
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/leds/common.h>
14 /include/ "fsl/p2020si-pre.dtsi"
41 gpio-controller@18 {
45 #gpio-cells = <2>;
46 gpio-controller;
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/linux-6.14.4/drivers/media/platform/ti/cal/
Dcal-camerarx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI Camera Access Layer (CAL) - CAMERARX
5 * Copyright (c) 2015-2020 Texas Instruments Inc.
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/v4l2-subdev.h>
28 /* ------------------------------------------------------------------
30 * ------------------------------------------------------------------
35 return ioread32(phy->base + offset); in camerarx_read()
40 iowrite32(val, phy->base + offset); in camerarx_write()
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/linux-6.14.4/drivers/usb/host/
Docteon-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks ([email protected]). All rights
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
131 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
133 * * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
172 * This value is in terms of 32-bit words.
211 * - ...
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/linux-6.14.4/arch/arm/boot/dts/nxp/ls/
Dls1021a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a7";
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/linux-6.14.4/drivers/net/ethernet/marvell/mvpp2/
Dmvpp2_main.c1 // SPDX-License-Identifier: GPL-2.0
76 writel(data, priv->swth_base[0] + offset); in mvpp2_write()
81 return readl(priv->swth_base[0] + offset); in mvpp2_read()
86 return readl_relaxed(priv->swth_base[0] + offset); in mvpp2_read_relaxed()
91 return cpu % priv->nthreads; in mvpp2_cpu_to_thread()
96 writel(data, priv->cm3_base + offset); in mvpp2_cm3_write()
101 return readl(priv->cm3_base + offset); in mvpp2_cm3_read()
124 * - per-thread registers, where each thread has its own copy of the
140 * - global registers that must be accessed through a specific thread
141 * window, because they are related to an access to a per-thread
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/linux-6.14.4/drivers/gpu/drm/omapdrm/dss/
Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
78 return dev_get_drvdata(dssdev->dev); in to_dsi_data()
92 case DSI_PROTO: base = dsi->proto_base; break; in dsi_write_reg()
93 case DSI_PHY: base = dsi->phy_base; break; in dsi_write_reg()
94 case DSI_PLL: base = dsi->pll_base; break; in dsi_write_reg()
106 case DSI_PROTO: base = dsi->proto_base; break; in dsi_read_reg()
107 case DSI_PHY: base = dsi->phy_base; break; in dsi_read_reg()
108 case DSI_PLL: base = dsi->pll_base; break; in dsi_read_reg()
117 down(&dsi->bus_lock); in dsi_bus_lock()
122 up(&dsi->bus_lock); in dsi_bus_unlock()
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