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Searched +full:sync +full:- +full:clk +full:- +full:ps (Results 1 – 25 of 77) sorted by relevance

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/linux-6.14.4/drivers/memory/
Dmvebu-devbus.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2013-2014 Marvell
14 #include <linux/clk.h>
96 dev_err(devbus->dev, "%pOF has no '%s' property\n", in get_timing_param_ps()
101 *ticks = (time_ps + devbus->tick_ps - 1) / devbus->tick_ps; in get_timing_param_ps()
103 dev_dbg(devbus->dev, "%s: %u ps -> 0x%x\n", in get_timing_param_ps()
115 err = of_property_read_u32(node, "devbus,bus-width", &r->bus_width); in devbus_get_timing_params()
117 dev_err(devbus->dev, in devbus_get_timing_params()
118 "%pOF has no 'devbus,bus-width' property\n", in devbus_get_timing_params()
127 if (r->bus_width == 8) { in devbus_get_timing_params()
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Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <[email protected]>
19 #include <linux/clk.h>
33 #include <linux/omap-gpmc.h>
37 #include <linux/platform_data/mtd-nand-omap2.h>
39 #define DEVICE_NAME "omap-gpmc"
258 /* Define chip-selects as reserved by default until probe completes */
264 static struct clk *gpmc_l3_clk;
306 * gpmc_get_clk_period - get period of selected clock domain in ps
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/linux-6.14.4/arch/arm/boot/dts/ti/omap/
Domap3-igep.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 /dts-v1/;
19 stdout-path = &uart3;
23 compatible = "ti,omap-twl4030";
28 vdd33: regulator-vdd33 {
29 compatible = "regulator-fixed";
30 regulator-name = "vdd33";
31 regulator-always-on;
37 gpmc_pins: gpmc-pins {
38 pinctrl-single,pins = <
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Domap2420-n8x0-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 stdout-path = &uart3;
16 compatible = "i2c-cbus-gpio";
17 gpios = <&gpio3 2 GPIO_ACTIVE_HIGH /* gpio66 clk */
21 #address-cells = <1>;
22 #size-cells = <0>;
25 interrupt-parent = <&gpio4>;
34 clock-frequency = <400000>;
44 clock-frequency = <400000>;
50 /* gpio-irq for dma: 26 */
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Domap3-gta04a5one.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-18 H. Nikolaus Schaller <[email protected]>
6 #include "omap3-gta04a5.dts"
13 gpmc_pins: gpmc-pins {
14 pinctrl-single,pins = <
45 pinctrl-names = "default";
46 pinctrl-0 = <&gpmc_pins>;
48 /delete-node/ nand@0,0;
52 #address-cells = <1>;
53 #size-cells = <1>;
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Domap4-duovero-parlor.dts1 // SPDX-License-Identifier: GPL-2.0-only
5 /dts-v1/;
7 #include "omap4-duovero.dtsi"
9 #include <dt-bindings/input/input.h>
13 compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4";
20 compatible = "gpio-leds";
24 linux,default-trigger = "heartbeat";
29 compatible = "gpio-keys";
30 #address-cells = <1>;
31 #size-cells = <0>;
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Domap2430-sdp.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
11 compatible = "ti,omap2430-sdp", "ti,omap2430", "ti,omap2";
20 clock-frequency = <100000>;
31 vmmc-supply = <&vmmc1>;
32 bus-width = <4>;
39 interrupt-parent = <&gpio5>;
42 bank-width = <2>;
43 gpmc,sync-clk-ps = <0>;
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Domap3-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "omap3-evm-common.dtsi"
9 #include "omap3-evm-processor-common.dtsi"
13 compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3";
17 pinctrl-names = "default";
18 pinctrl-0 = <&hsusb2_2_pins>;
20 ehci_phy_pins: ehci-phy-pins {
21 pinctrl-single,pins = <
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Domap3-evm-37xx.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "omap3-evm-common.dtsi"
9 #include "omap3-evm-processor-common.dtsi"
13 compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3";
17 pinctrl-names = "default";
18 pinctrl-0 = <&hsusb2_2_pins>;
20 ehci_phy_pins: ehci-phy-pins {
21 pinctrl-single,pins = <
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Ddm8148-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
2 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
9 compatible = "ti,dm8148-evm", "ti,dm8148", "ti,dm814";
18 compatible = "regulator-fixed";
19 regulator-name = "vmmcsd_fixed";
20 regulator-min-microvolt = <3300000>;
21 regulator-max-microvolt = <3300000>;
26 phy-handle = <&ethphy0>;
27 phy-mode = "rgmii-id";
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Ddra62x-j5eco-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
2 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
9 compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148", "ti,dm814";
18 compatible = "regulator-fixed";
19 regulator-name = "vmmcsd_fixed";
20 regulator-min-microvolt = <3300000>;
21 regulator-max-microvolt = <3300000>;
26 phy-handle = <&ethphy0>;
27 phy-mode = "rgmii-id";
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Dam335x-chilisom.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/
7 #include <dt-bindings/interrupt-controller/irq.h>
11 compatible = "grinn,am335x-chilisom", "ti,am33xx";
15 cpu0-supply = <&dcdc2_reg>;
26 pinctrl-names = "default";
28 i2c0_pins: i2c0-pins {
29 pinctrl-single,pins = <
35 nandflash_pins: nandflash-pins {
36 pinctrl-single,pins = <
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Dam335x-nano.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Newflow Ltd - https://www.newflow.co.uk/
5 /dts-v1/;
15 cpu0-supply = <&dcdc2_reg>;
25 compatible = "gpio-leds";
30 default-state = "off";
36 pinctrl-names = "default";
37 pinctrl-0 = <&misc_pins>;
39 misc_pins: misc-pins {
40 pinctrl-single,pins = <
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Dam335x-igep0033.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x
5 * Copyright (C) 2013 ISEE 2007 SL - https://www.isee.biz
8 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/irq.h>
16 cpu0-supply = <&vdd1_reg>;
26 pinctrl-names = "default";
27 pinctrl-0 = <&leds_pins>;
29 compatible = "gpio-leds";
34 default-state = "on";
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/linux-6.14.4/drivers/fpga/
Dzynq-fpga.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2015 Xilinx Inc.
10 #include <linux/clk.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/fpga/fpga-mgr.h>
113 /* Enable Level shifters from PS to PL */
115 /* Enable Level shifters from PL to PS */
124 struct clk *clk; member
140 writel(val, priv->io_base + offset); in zynq_fpga_write()
146 return readl(priv->io_base + offset); in zynq_fpga_read()
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/linux-6.14.4/drivers/video/fbdev/omap/
Dhwa742.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2004-2005 Nokia Corporation
14 #include <linux/clk.h>
86 struct completion *sync; member
130 struct clk *sys_ck;
139 hwa742.extif->set_bits_per_cycle(8); in hwa742_read_reg()
140 hwa742.extif->write_command(&reg, 1); in hwa742_read_reg()
141 hwa742.extif->read_data(&data, 1); in hwa742_read_reg()
148 hwa742.extif->set_bits_per_cycle(8); in hwa742_write_reg()
149 hwa742.extif->write_command(&reg, 1); in hwa742_write_reg()
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Dsossi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2004-2005 Nokia Corporation
10 #include <linux/clk.h>
15 #include <linux/omap-dma.h>
16 #include <linux/soc/ti/omap1-io.h>
22 #define MODULE_NAME "omapfb-sossi"
49 struct clk *fck;
114 static u32 ps_to_sossi_ticks(u32 ps, int div) in ps_to_sossi_ticks() argument
117 return (clk_period + ps - 1) / clk_period; in ps_to_sossi_ticks()
124 int div = t->clk_div; in calc_rd_timings()
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/linux-6.14.4/Documentation/devicetree/bindings/memory-controllers/
Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <[email protected]>
11 - Roger Quadros <[email protected]>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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/linux-6.14.4/drivers/net/ethernet/marvell/
Dmvneta.c7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
14 #include <linux/clk.h>
156 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
158 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
270 * to cover all rate-limit values from 10Kbps up to 5Gbps
300 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
378 #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD)
381 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
473 struct mvneta_stats ps; member
490 /* Pointer to the CPU-local NAPI struct */
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/linux-6.14.4/arch/arm64/boot/dts/ti/
Dk3-am62-lp-sk-nand.dtso1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include "k3-pinctrl.h"
17 gpmc0_pins_default: gpmc0-pins-default {
18 pinctrl-single,pins = <
44 pinctrl-names = "default";
45 pinctrl-0 = <&gpmc0_pins_default>;
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Dk3-am642-evm-nand.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include "k3-pinctrl.h"
15 gpmc0_default_pins: gpmc0-default-pins {
16 bootph-all;
17 pinctrl-single,pins = <
53 gpmc0-hog {
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/linux-6.14.4/drivers/phy/amlogic/
Dphy-meson-axg-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk.h>
33 * [11] mipi divider clk selection.
46 * [1] write 1 to sync the txclkesc input. the internal logic have to
52 /* [31] clk lane tx_hs_en control selection.
53 * 1: from register. 0: use clk lane state machine.
55 * [29] clk lane tx_lp_en contrl selection.
56 * 1: from register. 0: from clk lane state machine.
88 * [4] clk chan power down. this bit is also used as the power down
101 * [20:17] clk lane state. {mbias_ready, tx_stop, tx_ulps, tx_hs_active}
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/linux-6.14.4/drivers/input/serio/
Dps2-gpio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO based serio bus driver for bit banging the PS/2 protocol
5 * Author: Danilo Krummrich <danilokrummrich@dk-develop.de>
24 #define DRIVER_NAME "ps2-gpio"
50 * interrupt interval should be ~60us. Let's allow +/- 20us for frequency
61 * |-----------------| |--------|
68 #define PS2_IRQ_MIN_INTERVAL_US (PS2_CLK_MIN_INTERVAL_US - 20)
98 struct ps2_gpio_data *drvdata = serio->port_data; in ps2_gpio_open()
100 drvdata->t_irq_last = 0; in ps2_gpio_open()
101 drvdata->tx.t_xfer_end = 0; in ps2_gpio_open()
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/linux-6.14.4/drivers/gpu/drm/bridge/adv7511/
Dadv7511.h1 /* SPDX-License-Identifier: GPL-2.0-only */
62 #define ADV7511_REG_GC(x) (0x4b + (x)) /* 0x4b - 0x51 */
66 #define ADV7511_REG_AVI_INFOFRAME(x) (0x55 + (x)) /* 0x55 - 0x6f */
70 #define ADV7511_REG_AUDIO_INFOFRAME(x) (0x73 + (x)) /* 0x73 - 0x7c */
77 #define ADV7511_REG_AN(x) (0xb0 + (x)) /* 0xb0 - 0xb7 */
80 #define ADV7511_REG_BKSV(x) (0xc0 + (x)) /* 0xc0 - 0xc3 */
84 #define ADV7511_REG_BSTATUS(x) (0xca + (x)) /* 0xca - 0xcb */
89 #define ADV7511_REG_SYNC_ADJUSTMENT(x) (0xd7 + (x)) /* 0xd7 - 0xdc */
251 * enum adv7511_sync_polarity - Polarity for the input sync signals
252 * @ADV7511_SYNC_POLARITY_PASSTHROUGH: Sync polarity matches that of
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/linux-6.14.4/drivers/pwm/
Dpwm-sti.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2013-2016 STMicroelectronics (R&D) Limited
11 #include <linux/clk.h>
59 * Each capture input can be programmed to detect rising-edge, falling-edge,
78 struct clk *pwm_clk;
79 struct clk *cpt_clk;
95 struct mutex sti_pwm_lock; /* To sync between enable/disable calls */
122 unsigned int ps; in sti_pwm_get_prescale() local
124 clk_rate = clk_get_rate(pc->pwm_clk); in sti_pwm_get_prescale()
126 dev_err(pc->dev, "failed to get clock rate\n"); in sti_pwm_get_prescale()
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