Searched +full:ssc +full:- +full:modfreq +full:- +full:hz (Results 1 – 4 of 4) sorted by relevance
| /linux-6.14.4/Documentation/devicetree/bindings/clock/ |
| D | st,stm32-rcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/st,stm32-rcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dario Binacchi <[email protected]>
20 - items:
21 - enum:
22 - st,stm32f42xx-rcc
23 - st,stm32f746-rcc
24 - st,stm32h743-rcc
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| /linux-6.14.4/Documentation/devicetree/bindings/clock/ti/ |
| D | dpll.txt | 4 register-mapped DPLL with usually two selectable input clocks
9 sub-types, which effectively result in slightly different setup
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible : shall be one of:
16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-clock",
20 "ti,omap4-dpll-clock",
21 "ti,omap4-dpll-x2-clock",
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| /linux-6.14.4/drivers/clk/ti/ |
| D | dpll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * Tero Kristo <t-[email protected]>
11 #include <linux/clk-provider.h>
143 * _register_dpll - low level registration of a DPLL clock
147 * Finalizes DPLL registration process. In case a failure (clk-ref or
148 * clk-bypass is missing), the clock is added to retry list and
156 struct dpll_data *dd = clk_hw->dpll_data; in _register_dpll()
159 const struct clk_init_data *init = hw->init; in _register_dpll()
163 pr_debug("clk-ref missing for %pOFn, retry later\n", in _register_dpll()
171 dd->clk_ref = __clk_get_hw(clk); in _register_dpll()
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| /linux-6.14.4/drivers/clk/ |
| D | clk-stm32f4.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Inspired by clk-asm9260.c .
9 #include <linux/clk-provider.h>
26 #include <dt-bindings/clock/stm32fx-clock.h>
52 #define NONE -1
383 [STM32F4_PLL_SSC_DOWN_SPREAD] = "down-spread",
384 [STM32F4_PLL_SSC_CENTER_SPREAD] = "center-spread",
423 * The APBx dividers are power-of-two dividers and, if *not* running in 1:1
440 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_recalc_rate()
452 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_round_rate()
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