1 // SPDX-License-Identifier: GPL-2.0-only
7  * Tero Kristo <t-[email protected]>
11 #include <linux/clk-provider.h>
143  * _register_dpll - low level registration of a DPLL clock
147  * Finalizes DPLL registration process. In case a failure (clk-ref or
148  * clk-bypass is missing), the clock is added to retry list and
156 	struct dpll_data *dd = clk_hw->dpll_data;  in _register_dpll()
159 	const struct clk_init_data *init = hw->init;  in _register_dpll()
163 		pr_debug("clk-ref missing for %pOFn, retry later\n",  in _register_dpll()
171 	dd->clk_ref = __clk_get_hw(clk);  in _register_dpll()
176 		pr_debug("clk-bypass missing for %pOFn, retry later\n",  in _register_dpll()
184 	dd->clk_bypass = __clk_get_hw(clk);  in _register_dpll()
188 	clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);  in _register_dpll()
192 		kfree(init->parent_names);  in _register_dpll()
198 	kfree(clk_hw->dpll_data);  in _register_dpll()
199 	kfree(init->parent_names);  in _register_dpll()
208  * _register_dpll_x2 - Registers a DPLLx2 clock
235 	clk_hw->ops = hw_ops;  in _register_dpll_x2()
236 	clk_hw->hw.init = &init;  in _register_dpll_x2()
248 		/* Check if register defined, if not, drop hw-ops */  in _register_dpll_x2()
251 			clk_hw->ops = NULL;  in _register_dpll_x2()
252 		} else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) {  in _register_dpll_x2()
260 	clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);  in _register_dpll_x2()
270  * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
295 	clk_hw->dpll_data = dd;  in of_ti_dpll_setup()
296 	clk_hw->ops = &clkhwops_omap3_dpll;  in of_ti_dpll_setup()
297 	clk_hw->hw.init = init;  in of_ti_dpll_setup()
299 	init->name = ti_dt_clk_name(node);  in of_ti_dpll_setup()
300 	init->ops = ops;  in of_ti_dpll_setup()
302 	init->num_parents = of_clk_get_parent_count(node);  in of_ti_dpll_setup()
303 	if (!init->num_parents) {  in of_ti_dpll_setup()
308 	parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL);  in of_ti_dpll_setup()
312 	of_clk_parent_fill(node, parent_names, init->num_parents);  in of_ti_dpll_setup()
314 	init->parent_names = parent_names;  in of_ti_dpll_setup()
316 	if (ti_clk_get_reg_addr(node, 0, &dd->control_reg))  in of_ti_dpll_setup()
324 	if (!dd->idlest_mask) {  in of_ti_dpll_setup()
325 		if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg))  in of_ti_dpll_setup()
328 		clk_hw->ops = &clkhwops_omap2xxx_dpll;  in of_ti_dpll_setup()
329 		omap2xxx_clkt_dpllcore_init(&clk_hw->hw);  in of_ti_dpll_setup()
332 		if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg))  in of_ti_dpll_setup()
335 		if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg))  in of_ti_dpll_setup()
339 	if (dd->autoidle_mask) {  in of_ti_dpll_setup()
340 		if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg))  in of_ti_dpll_setup()
348 	if (dd->ssc_deltam_int_mask && dd->ssc_deltam_frac_mask &&  in of_ti_dpll_setup()
349 	    dd->ssc_modfreq_mant_mask && dd->ssc_modfreq_exp_mask) {  in of_ti_dpll_setup()
351 					&dd->ssc_deltam_reg))  in of_ti_dpll_setup()
355 					&dd->ssc_modfreq_reg))  in of_ti_dpll_setup()
358 		of_property_read_u32(node, "ti,ssc-modfreq-hz",  in of_ti_dpll_setup()
359 				     &dd->ssc_modfreq);  in of_ti_dpll_setup()
360 		of_property_read_u32(node, "ti,ssc-deltam", &dd->ssc_deltam);  in of_ti_dpll_setup()
361 		dd->ssc_downspread =  in of_ti_dpll_setup()
362 			of_property_read_bool(node, "ti,ssc-downspread");  in of_ti_dpll_setup()
365 	if (of_property_read_bool(node, "ti,low-power-stop"))  in of_ti_dpll_setup()
368 	if (of_property_read_bool(node, "ti,low-power-bypass"))  in of_ti_dpll_setup()
374 	if (!of_property_read_u32(node, "ti,min-div", &min_div) &&  in of_ti_dpll_setup()
375 	    min_div > dd->min_divider)  in of_ti_dpll_setup()
376 		dd->min_divider = min_div;  in of_ti_dpll_setup()
379 		dd->modes = dpll_mode;  in of_ti_dpll_setup()
381 	_register_dpll(&clk_hw->hw, node);  in of_ti_dpll_setup()
397 CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
406 CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
433 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
452 CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
472 CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
494 CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
514 CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
535 CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
554 CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
577 CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
598 CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
624 CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
644 CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
665 	       "ti,am3-dpll-no-gate-j-type-clock",
690 CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
708 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
723 CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",