Searched +full:spi +full:- +full:num +full:- +full:cs (Results 1 – 25 of 339) sorted by relevance
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/linux-6.14.4/Documentation/devicetree/bindings/spi/ |
D | fsl,dspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/fsl,dspi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Frank Li <[email protected]> 15 - enum: 16 - fsl,vf610-dspi 17 - fsl,ls1021a-v1.0-dspi 18 - fsl,ls1012a-dspi 19 - fsl,ls1028a-dspi [all …]
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D | spi-lantiq-ssc.txt | 1 Lantiq Synchronous Serial Controller (SSC) SPI master driver 4 - compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi", 5 "intel,lgm-spi" 6 - #address-cells: see spi-bus.txt 7 - #size-cells: see spi-bus.txt 8 - reg: address and length of the spi master registers 9 - interrupts: 10 For compatible "intel,lgm-ssc" - the common interrupt number for 18 - clocks: spi clock phandle 19 - num-cs: see spi-bus.txt, set to 8 if unset [all …]
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D | spi-cadence.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/spi-cadence.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Cadence SPI controller 10 - Michal Simek <[email protected]> 13 - $ref: spi-controller.yaml# 18 - cdns,spi-r1p6 19 - xlnx,zynq-spi-r1p6 27 clock-names: [all …]
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D | spi-davinci.txt | 1 Davinci SPI controller device bindings 4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf 5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf 6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf 9 - #address-cells: number of cells required to define a chip select 10 address on the SPI bus. Should be set to 1. 11 - #size-cells: should be zero. 12 - compatible: 13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family 14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family [all …]
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D | spi-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/spi/spi-gpio.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: SPI-GPIO 10 - Rob Herring <[email protected]> 13 This represents a group of 3-n GPIO lines used for bit-banged SPI on 17 - $ref: /schemas/spi/spi-controller.yaml# 21 const: spi-gpio 23 sck-gpios: [all …]
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D | microchip,mpfs-spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Microchip FPGA {Q,}SPI Controllers 10 SPI and QSPI controllers on Microchip PolarFire SoC and the "soft"/ 14 - Conor Dooley <[email protected]> 19 - items: 20 - enum: 21 - microchip,mpfs-qspi [all …]
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D | samsung,spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/samsung,spi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Samsung S3C/S5P/Exynos SoC SPI controller 10 - Krzysztof Kozlowski <[email protected]> 13 All the SPI controller nodes should be represented in the aliases node using 14 the following format 'spi{n}' where n is a unique number for the alias. 19 - enum: 20 - google,gs101-spi [all …]
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D | spi-fsl-lpspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Freescale Low Power SPI (LPSPI) for i.MX 10 - Shawn Guo <[email protected]> 11 - Sascha Hauer <[email protected]> 12 - Fabio Estevam <[email protected]> 15 - $ref: /schemas/spi/spi-controller.yaml# 20 - enum: [all …]
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D | fsl-spi.txt | 1 * SPI (Serial Peripheral Interface) 4 - cell-index : QE SPI subblock index. 7 - compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl". 8 - mode : the SPI operation mode, it can be "cpu" or "cpu-qe". 9 - reg : Offset and length of the register set for the device 10 - interrupts : <a b> where a is the interrupt number and b is a 15 - clock-frequency : input clock frequency to non FSL_SOC cores 18 - cs-gpios : specifies the gpio pins to be used for chipselects. 19 The gpios will be referred to as reg = <index> in the SPI child nodes. 20 If unspecified, a single SPI device without a chip select can be used. [all …]
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D | marvell,armada-3700-spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/marvell,armada-3700-spi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Marvell Armada 3700 SPI Controller 10 The SPI controller on Marvell Armada 3700 SoC. 13 - Kousik Sanagavarapu <[email protected]> 16 - $ref: spi-controller.yaml# 20 const: marvell,armada-3700-spi 31 num-cs: [all …]
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D | socionext,f-ospi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/socionext,f-ospi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 memories using the SPI communication interface. 14 - Kunihiko Hayashi <[email protected]> 17 - $ref: spi-controller.yaml# 21 const: socionext,f-ospi 29 num-cs: 34 - compatible [all …]
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D | snps,dw-apb-ssi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Mark Brown <[email protected]> 13 - $ref: spi-controller.yaml# 14 - if: 19 - mscc,ocelot-spi 20 - mscc,jaguar2-spi 25 - if: [all …]
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D | ti,qspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/ti,qspi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Kousik Sanagavarapu <[email protected]> 13 - $ref: spi-controller.yaml# 18 - ti,am4372-qspi 19 - ti,dra7xxx-qspi 23 - description: base registers 24 - description: mapped memory [all …]
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D | spi-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: SPI Controller Common Properties 10 - Mark Brown <[email protected]> 13 SPI busses can be described with a node for the SPI controller device 14 and a set of child nodes for each SPI slave on the bus. The system SPI 15 controller may be described for use in SPI master mode or in SPI slave mode, 20 pattern: "^spi(@.*|-([0-9]|[1-9][0-9]+))?$" [all …]
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D | brcm,spi-bcm-qspi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Broadcom SPI controller 10 - Kamal Dasu <[email protected]> 11 - Rafał Miłecki <[email protected]> 14 The Broadcom SPI controller is a SPI master found on various SOCs, including 15 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists 17 MSPI : SPI master controller can read and write to a SPI slave device [all …]
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/linux-6.14.4/arch/riscv/boot/dts/canaan/ |
D | sipeed_maix_bit.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2019-20 Sean Anderson <[email protected]> 7 /dts-v1/; 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/input.h> 13 #include <dt-bindings/leds/common.h> 17 compatible = "sipeed,maix-bit", "sipeed,maix-bitm", 18 "canaan,kendryte-k210"; 26 stdout-path = "serial0:115200n8"; 29 gpio-leds { [all …]
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D | sipeed_maix_dock.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2019-20 Sean Anderson <[email protected]> 7 /dts-v1/; 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/input.h> 13 #include <dt-bindings/leds/common.h> 17 compatible = "sipeed,maix-dock-m1", "sipeed,maix-dock-m1w", 18 "canaan,kendryte-k210"; 26 stdout-path = "serial0:115200n8"; 29 gpio-leds { [all …]
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D | sipeed_maix_go.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2019-20 Sean Anderson <[email protected]> 7 /dts-v1/; 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/input.h> 13 #include <dt-bindings/leds/common.h> 17 compatible = "sipeed,maix-go", "canaan,kendryte-k210"; 25 stdout-path = "serial0:115200n8"; 28 gpio-leds { 29 compatible = "gpio-leds"; [all …]
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D | sipeed_maixduino.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2019-20 Sean Anderson <[email protected]> 7 /dts-v1/; 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/input.h> 16 compatible = "sipeed,maixduino", "canaan,kendryte-k210"; 24 stdout-path = "serial0:115200n8"; 27 gpio-keys { 28 compatible = "gpio-keys"; 30 key-boot { [all …]
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D | canaan_kd233.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2019-20 Sean Anderson <[email protected]> 7 /dts-v1/; 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/input.h> 16 compatible = "canaan,kendryte-kd233", "canaan,kendryte-k210"; 24 stdout-path = "serial0:115200n8"; 27 gpio-leds { 28 compatible = "gpio-leds"; 39 gpio-keys { [all …]
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/linux-6.14.4/Documentation/devicetree/bindings/gpio/ |
D | spear_spics.txt | 1 === ST Microelectronics SPEAr SPI CS Driver === 4 Cell spi controller through its system registers, which otherwise remains under 7 desired by some of the device protocols above spi which expect (multiple) 17 * compatible: should be defined as "st,spear-spics-gpio" 19 * st-spics,peripcfg-reg: peripheral configuration register offset 20 * st-spics,sw-enable-bit: bit offset to enable sw control 21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high 22 * st-spics,cs-enable-mask: chip select number bit mask 23 * st-spics,cs-enable-shift: chip select number program offset 24 * gpio-controller: Marks the device node as gpio controller [all …]
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/linux-6.14.4/arch/arm64/boot/dts/toshiba/ |
D | tmpv7708.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 * (C) Copyright 2018 - 2020, Toshiba Corporation. 10 #include <dt-bindings/clock/toshiba,tmpv770x.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ 18 #address-cells = <2>; 19 #size-cells = <2>; 22 #address-cells = <1>; 23 #size-cells = <0>; [all …]
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/linux-6.14.4/arch/arm64/boot/dts/freescale/ |
D | fsl-ls1043a-rdb.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for Freescale Layerscape-1043A family SoC. 5 * Copyright 2014-2015 Freescale Semiconductor, Inc. 11 /dts-v1/; 12 #include "fsl-ls1043a.dtsi" 16 compatible = "fsl,ls1043a-rdb", "fsl,ls1043a"; 26 stdout-path = "serial0:115200n8"; 36 shunt-resistor = <1000>; 67 #address-cells = <2>; 68 #size-cells = <1>; [all …]
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/linux-6.14.4/arch/arm/boot/dts/hisilicon/ |
D | hi3519.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 #include <dt-bindings/clock/hi3519-clock.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #address-cells = <1>; 10 #size-cells = <1>; 14 #address-cells = <1>; 15 #size-cells = <0>; 19 compatible = "arm,cortex-a7"; 24 gic: interrupt-controller@10300000 { 25 compatible = "arm,cortex-a7-gic"; [all …]
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/linux-6.14.4/arch/arm64/boot/dts/exynos/ |
D | exynosautov9.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 9 #include <dt-bindings/clock/samsung,exynosautov9.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/soc/samsung,boot-mode.h> 12 #include <dt-bindings/soc/samsung,exynos-usi.h> 16 #address-cells = <2>; 17 #size-cells = <1>; 19 interrupt-parent = <&gic>; 31 arm-pmu { 32 compatible = "arm,cortex-a76-pmu"; [all …]
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