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/linux-6.14.4/drivers/net/ethernet/microchip/sparx5/
Dsparx5_vcap_impl.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver VCAP implementation
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
50 .vtype = VCAP_TYPE_IS0, /* CLM-0 */
56 .last_cid = SPARX5_VCAP_CID_IS0_L2 - 1,
57 .blockno = 8, /* Maps block 8-9 */
62 .vtype = VCAP_TYPE_IS0, /* CLM-1 */
68 .last_cid = SPARX5_VCAP_CID_IS0_L4 - 1,
69 .blockno = 6, /* Maps block 6-7 */
[all …]
Dsparx5_switchdev.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
19 struct sparx5 *sparx5; member
27 return -EINVAL; in sparx5_port_attr_pre_bridge_flags()
34 bool should_flood = flood_flag || port->is_mrouter; in sparx5_port_update_mcast_ip_flood()
35 struct sparx5 *sparx5 = port->sparx5; in sparx5_port_update_mcast_ip_flood() local
38 for (pgid = sparx5_get_pgid(sparx5, PGID_IPV4_MC_DATA); in sparx5_port_update_mcast_ip_flood()
39 pgid <= sparx5_get_pgid(sparx5, PGID_IPV6_MC_CTRL); pgid++) in sparx5_port_update_mcast_ip_flood()
46 struct sparx5 *sparx5 = port->sparx5; in sparx5_port_attr_bridge_flags() local
50 sparx5_get_pgid(sparx5, PGID_MC_FLOOD), in sparx5_port_attr_bridge_flags()
[all …]
Dsparx5_main.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
215 bool is_sparx5(struct sparx5 *sparx5) in is_sparx5() argument
217 switch (sparx5->target_ct) { in is_sparx5()
234 static void sparx5_init_features(struct sparx5 *sparx5) in sparx5_init_features() argument
236 switch (sparx5->target_ct) { in sparx5_init_features()
256 sparx5->features = (SPX5_FEATURE_PSFP | SPX5_FEATURE_PTP); in sparx5_init_features()
263 bool sparx5_has_feature(struct sparx5 *sparx5, enum sparx5_feature feature) in sparx5_has_feature() argument
[all …]
Dsparx5_vcap_debugfs.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver VCAP debugFS implementation
18 switch (value) { in sparx5_vcap_is0_etype_str()
42 switch (value) { in sparx5_vcap_is0_mpls_str()
66 switch (value) { in sparx5_vcap_is0_mlbs_str()
76 static void sparx5_vcap_is0_port_keys(struct sparx5 *sparx5, in sparx5_vcap_is0_port_keys() argument
84 out->prf(out->dst, " port[%02d] (%s): ", port->portno, in sparx5_vcap_is0_port_keys()
85 netdev_name(port->ndev)); in sparx5_vcap_is0_port_keys()
86 for (lookup = 0; lookup < admin->lookups; ++lookup) { in sparx5_vcap_is0_port_keys()
87 out->prf(out->dst, "\n Lookup %d: ", lookup); in sparx5_vcap_is0_port_keys()
[all …]
Dsparx5_port.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
31 status->an_complete = true; in decode_sgmii_word()
33 status->link = false; in decode_sgmii_word()
37 switch (lp_abil & LPA_SGMII_SPD_MASK) { in decode_sgmii_word()
39 status->speed = SPEED_10; in decode_sgmii_word()
42 status->speed = SPEED_100; in decode_sgmii_word()
45 status->speed = SPEED_1000; in decode_sgmii_word()
48 status->link = false; in decode_sgmii_word()
52 status->duplex = DUPLEX_FULL; in decode_sgmii_word()
[all …]
Dsparx5_ptp.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
25 static u64 sparx5_ptp_get_1ppm(struct sparx5 *sparx5) in sparx5_ptp_get_1ppm() argument
30 * (1/1000000)/((2^-59)/X) in sparx5_ptp_get_1ppm()
35 switch (sparx5->coreclock) { in sparx5_ptp_get_1ppm()
56 static u64 sparx5_ptp_get_nominal_value(struct sparx5 *sparx5) in sparx5_ptp_get_nominal_value() argument
60 switch (sparx5->coreclock) { in sparx5_ptp_get_nominal_value()
85 struct sparx5 *sparx5 = port->sparx5; in sparx5_ptp_hwtstamp_set() local
[all …]
Dsparx5_calendar.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
37 static u32 sparx5_target_bandwidth(struct sparx5 *sparx5) in sparx5_target_bandwidth() argument
39 switch (sparx5->target_ct) { in sparx5_target_bandwidth()
78 switch (cclock) { in sparx5_clk_to_bandwidth()
90 switch (speed) { in sparx5_cal_speed_to_value()
104 switch (bw) { in sparx5_bandwidth_to_calendar()
118 enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, u32 portno) in sparx5_get_port_cal_speed() argument
122 if (portno >= sparx5->data->consts->n_ports) { in sparx5_get_port_cal_speed()
125 sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0) || in sparx5_get_port_cal_speed()
[all …]
Dsparx5_police.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
10 static int sparx5_policer_service_conf_set(struct sparx5 *sparx5, in sparx5_policer_service_conf_set() argument
14 const struct sparx5_ops *ops = sparx5->data->ops; in sparx5_policer_service_conf_set()
18 g = ops->get_sdlb_group(pol->group); in sparx5_policer_service_conf_set()
19 idx = pol->idx; in sparx5_policer_service_conf_set()
21 rate = pol->rate * 1000; in sparx5_policer_service_conf_set()
22 burst = pol->burst; in sparx5_policer_service_conf_set()
24 pup_tokens = sparx5_sdlb_pup_token_get(sparx5, g->pup_interval, rate); in sparx5_policer_service_conf_set()
26 sparx5_sdlb_pup_token_get(sparx5, g->pup_interval, g->max_rate); in sparx5_policer_service_conf_set()
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
3 # Makefile for the Microchip Sparx5 network device drivers.
6 obj-$(CONFIG_SPARX5_SWITCH) += sparx5-switch.o
8 sparx5-switch-y := sparx5_main.o sparx5_packet.o \
16 sparx5-switch-$(CONFIG_SPARX5_DCB) += sparx5_dcb.o
17 sparx5-switch-$(CONFIG_DEBUG_FS) += sparx5_vcap_debugfs.o
19 sparx5-switch-$(CONFIG_LAN969X_SWITCH) += lan969x/lan969x_regs.o \
28 ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/vcap
29 ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma
Dsparx5_tc_matchall.c1 // SPDX-License-Identifier: GPL-2.0+
20 if (entry->cookie == cookie) in sparx5_tc_matchall_entry_find()
33 entry->port = port; in sparx5_tc_matchall_parse_action()
34 entry->type = action->id; in sparx5_tc_matchall_parse_action()
35 entry->ingress = ingress; in sparx5_tc_matchall_parse_action()
36 entry->cookie = cookie; in sparx5_tc_matchall_parse_action()
43 entry->mirror.port = netdev_priv(action->dev); in sparx5_tc_matchall_parse_mirror_action()
53 struct sparx5 *sparx5; in sparx5_tc_matchall_replace() local
56 if (!flow_offload_has_one_action(&tmo->rule->action)) { in sparx5_tc_matchall_replace()
57 NL_SET_ERR_MSG_MOD(tmo->common.extack, in sparx5_tc_matchall_replace()
[all …]
Dsparx5_packet.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
19 #define XTR_VALID_BYTES(x) (4 - ((x) & 3))
23 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp) in sparx5_xtr_flush() argument
26 spx5_wr(QS_XTR_FLUSH_FLUSH_SET(BIT(grp)), sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
32 spx5_wr(0, sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
35 void sparx5_ifh_parse(struct sparx5 *sparx5, u32 *ifh, struct frame_info *info) in sparx5_ifh_parse() argument
39 /* FWD is bit 45-72 (28 bits), but we only read the 27 LSB for now */ in sparx5_ifh_parse()
46 info->src_port = spx5_field_get(GENMASK(is_sparx5(sparx5) ? 7 : 6, 1), in sparx5_ifh_parse()
50 * Bit 270-271 are occasionally unexpectedly set by the hardware, in sparx5_ifh_parse()
[all …]
Dsparx5_main.h1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Microchip Sparx5 Switch driver
29 SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */
30 SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */
31 SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */
32 SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */
33 SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */
34 SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */
35 SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */
36 SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */
[all …]
Dsparx5_port.h1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Microchip Sparx5 Switch driver
48 static inline u32 sparx5_to_high_dev(struct sparx5 *sparx5, int port) in sparx5_to_high_dev() argument
50 const struct sparx5_ops *ops = sparx5->data->ops; in sparx5_to_high_dev()
52 if (ops->is_port_5g(port)) in sparx5_to_high_dev()
54 if (ops->is_port_10g(port)) in sparx5_to_high_dev()
59 static inline u32 sparx5_to_pcs_dev(struct sparx5 *sparx5, int port) in sparx5_to_pcs_dev() argument
61 const struct sparx5_ops *ops = sparx5->data->ops; in sparx5_to_pcs_dev()
63 if (ops->is_port_5g(port)) in sparx5_to_pcs_dev()
65 if (ops->is_port_10g(port)) in sparx5_to_pcs_dev()
[all …]
Dsparx5_mirror.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
24 static u64 sparx5_mirror_port_get(struct sparx5 *sparx5, u32 idx) in sparx5_mirror_port_get() argument
28 val = spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG(idx)); in sparx5_mirror_port_get()
30 if (is_sparx5(sparx5)) in sparx5_mirror_port_get()
31 val |= (u64)spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG1(idx)) << 32; in sparx5_mirror_port_get()
37 static void sparx5_mirror_port_add(struct sparx5 *sparx5, u32 idx, u32 portno) in sparx5_mirror_port_add() argument
45 return spx5_rmw(val, val, sparx5, ANA_AC_PROBE_PORT_CFG(idx)); in sparx5_mirror_port_add()
47 return spx5_rmw(val, val, sparx5, ANA_AC_PROBE_PORT_CFG1(idx)); in sparx5_mirror_port_add()
51 static void sparx5_mirror_port_del(struct sparx5 *sparx5, u32 idx, u32 portno) in sparx5_mirror_port_del() argument
[all …]
Dsparx5_vlan.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
10 static int sparx5_vlant_set_mask(struct sparx5 *sparx5, u16 vid) in sparx5_vlant_set_mask() argument
15 bitmap_to_arr32(mask, sparx5->vlan_mask[vid], SPX5_PORTS); in sparx5_vlant_set_mask()
18 spx5_wr(mask[0], sparx5, ANA_L3_VLAN_MASK_CFG(vid)); in sparx5_vlant_set_mask()
19 if (is_sparx5(sparx5)) { in sparx5_vlant_set_mask()
20 spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid)); in sparx5_vlant_set_mask()
21 spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid)); in sparx5_vlant_set_mask()
27 void sparx5_vlan_init(struct sparx5 *sparx5) in sparx5_vlan_init() argument
33 sparx5, in sparx5_vlan_init()
[all …]
Dsparx5_sdlb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
28 u64 sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5) in sparx5_sdlb_clk_hz_get() argument
33 (sparx5_clk_period(sparx5->coreclock) / 100); in sparx5_sdlb_clk_hz_get()
38 static int sparx5_sdlb_pup_interval_get(struct sparx5 *sparx5, u32 max_token, in sparx5_sdlb_pup_interval_get() argument
43 clk_hz = sparx5_sdlb_clk_hz_get(sparx5); in sparx5_sdlb_pup_interval_get()
48 int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval, u64 rate) in sparx5_sdlb_pup_token_get() argument
55 clk_hz = sparx5_sdlb_clk_hz_get(sparx5); in sparx5_sdlb_pup_token_get()
60 static void sparx5_sdlb_group_disable(struct sparx5 *sparx5, u32 group) in sparx5_sdlb_group_disable() argument
63 ANA_AC_SDLB_PUP_CTRL_PUP_ENA, sparx5, in sparx5_sdlb_group_disable()
[all …]
Dsparx5_psfp.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
23 static int sparx5_psfp_sf_get(struct sparx5 *sparx5, u32 *id) in sparx5_psfp_sf_get() argument
26 sparx5->data->consts->n_filters, id); in sparx5_psfp_sf_get()
29 static int sparx5_psfp_sf_put(struct sparx5 *sparx5, u32 id) in sparx5_psfp_sf_put() argument
32 sparx5->data->consts->n_filters, id); in sparx5_psfp_sf_put()
35 static int sparx5_psfp_sg_get(struct sparx5 *sparx5, u32 idx, u32 *id) in sparx5_psfp_sg_get() argument
38 sparx5->data->consts->n_gates, idx, id); in sparx5_psfp_sg_get()
41 static int sparx5_psfp_sg_put(struct sparx5 *sparx5, u32 id) in sparx5_psfp_sg_put() argument
44 sparx5->data->consts->n_gates, id); in sparx5_psfp_sg_put()
[all …]
Dsparx5_tc_flower.c1 // SPDX-License-Identifier: GPL-2.0+
39 /* SparX-5 VCAP fragment types:
41 * 2 = suspicious fragment, 3 = valid follow-up fragment
57 /* 0/0 0/1 1/0 1/1 <-- first_frag */
65 switch (st->tpid) { in sparx5_tc_flower_es0_tpid()
67 err = vcap_rule_add_key_u32(st->vrule, in sparx5_tc_flower_es0_tpid()
72 err = vcap_rule_add_key_u32(st->vrule, in sparx5_tc_flower_es0_tpid()
77 NL_SET_ERR_MSG_MOD(st->fco->common.extack, in sparx5_tc_flower_es0_tpid()
79 err = -EINVAL; in sparx5_tc_flower_es0_tpid()
91 flow_rule_match_basic(st->frule, &mt); in sparx5_tc_flower_handler_basic_usage()
[all …]
Dsparx5_netdev.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
21 /* Max width is 5 bytes - 40 bits. In worst case this will
22 * spread over 6 bytes - 48 bits
33 u32 byte = (35 - (pos / 8)); in __ifh_encode_bitfield()
36 u64 encode = GENMASK_ULL(bit + width - 1, bit) & (value << bit); in __ifh_encode_bitfield()
38 /* The b0-b7 goes into the start IFH byte */ in __ifh_encode_bitfield()
41 /* The b8-b15 goes into the next IFH byte */ in __ifh_encode_bitfield()
43 ifh_hdr[byte - 1] |= (u8)((encode & 0xFF00) >> 8); in __ifh_encode_bitfield()
44 /* The b16-b23 goes into the next IFH byte */ in __ifh_encode_bitfield()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/arm/
Dmicrochip,sparx5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Sparx5 Boards
10 - Lars Povlsen <[email protected]>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
[all …]
/linux-6.14.4/arch/arm64/boot/dts/microchip/
Dsparx5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
11 compatible = "microchip,sparx5";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <1>;
23 stdout-path = "serial0:115200n8";
27 #address-cells = <1>;
[all …]
/linux-6.14.4/drivers/net/ethernet/microchip/sparx5/lan969x/
Dlan969x.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip lan969x Switch driver
123 static u32 lan969x_get_dev_mode_bit(struct sparx5 *sparx5, int port) in lan969x_get_dev_mode_bit() argument
129 switch (port) { in lan969x_get_dev_mode_bit()
143 static u32 lan969x_port_dev_mapping(struct sparx5 *sparx5, int port) in lan969x_port_dev_mapping() argument
146 switch (port) { in lan969x_port_dev_mapping()
159 switch (port) { in lan969x_port_dev_mapping()
187 static int lan969x_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port, in lan969x_port_mux_set() argument
190 u32 portno = port->portno; in lan969x_port_mux_set()
193 if (port->conf.portmode == conf->portmode) in lan969x_port_mux_set()
[all …]
Dlan969x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Microchip lan969x Switch driver
10 #include "../sparx5/sparx5_main.h"
11 #include "../sparx5/sparx5_regs.h"
12 #include "../sparx5/sparx5_vcap_impl.h"
68 int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi,
76 int lan969x_fdma_init(struct sparx5 *sparx5);
77 int lan969x_fdma_deinit(struct sparx5 *sparx5);
79 int lan969x_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb,
Dlan969x_rgmii.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip lan969x Switch driver
32 #define RGMII_PORT_IDX(port) ((port)->portno - LAN969X_RGMII_PORT_START_IDX)
54 switch (delay_ps) { in lan969x_rgmii_get_clk_delay_sel()
78 dev_err(port->sparx5->dev, "Invalid RGMII delay: %u", delay_ps); in lan969x_rgmii_get_clk_delay_sel()
79 return -EINVAL; in lan969x_rgmii_get_clk_delay_sel()
89 u32 clk_sel = lan969x_rgmii_get_clk_sel(conf->speed); in lan969x_rgmii_tx_clk_config()
101 port->sparx5, HSIO_WRAP_RGMII_CFG(idx)); in lan969x_rgmii_tx_clk_config()
110 speed_sel = lan969x_rgmii_get_speed_sel(conf->speed); in lan969x_rgmii_port_device_config()
112 etype = (port->vlan_type == SPX5_VLAN_PORT_TYPE_S_CUSTOM ? in lan969x_rgmii_port_device_config()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/reset/
Dmicrochip,rst.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Sparx5 Switch Reset Controller
10 - Steen Hegelund <[email protected]>
11 - Lars Povlsen <[email protected]>
14 The Microchip Sparx5 Switch provides reset control and implements the following
16 - One Time Switch Core Reset (Soft Reset)
20 pattern: "^reset-controller@[0-9a-f]+$"
24 - microchip,sparx5-switch-reset
[all …]

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