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/linux-6.14.4/Documentation/devicetree/bindings/iommu/
Dqcom,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <[email protected]>
13 Qualcomm "B" family devices which are not compatible with arm-smmu have
14 a similar looking IOMMU, but without access to the global register space
16 to non-secure vs secure interrupt line.
21 - items:
22 - enum:
23 - qcom,msm8916-iommu
[all …]
Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <[email protected]>
11 - Robin Murphy <[email protected]>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/bus/
Dst,stm32mp25-rifsc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gatien Chevallier <[email protected]>
19 - RISC registers associated with RISUP logic (resource isolation device unit
20 for peripherals), assign all non-RIF aware peripherals to zero, one or
21 any security domains (secure, privilege, compartment).
22 - RIMC registers: associated with RIMU logic (resource isolation master
23 unit), assign all non RIF-aware bus master to one security domain by
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra194-cbb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sumit Gupta <[email protected]>
15 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
20 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
23 By default, the access issuing initiator is informed about the error
28 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
31 - For other initiators, the ERD is disabled. So, the access issuing
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/nvmem/
Dst,stm32-romem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Factory-programmed data
10 This represents STM32 Factory-programmed read only non-volatile area: locked
11 flash, OTP, read-only HW regs... This contains various information such as:
16 - Fabrice Gasnier <[email protected]>
19 - $ref: nvmem.yaml#
20 - $ref: nvmem-deprecated-cells.yaml#
[all …]
Dqcom,sec-qfprom.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/qcom,sec-qfprom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies Inc, Secure QFPROM Efuse
10 - Komal Bajaj <[email protected]>
14 protected from non-secure access. In such situations, the OS have to use
15 secure calls to read the region.
18 - $ref: nvmem.yaml#
19 - $ref: nvmem-deprecated-cells.yaml#
[all …]
/linux-6.14.4/drivers/nvmem/
Dsec-qfprom.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/nvmem-provider.h>
13 * struct sec_qfprom - structure holding secure qfprom attributes
15 * @base: starting physical address for secure qfprom corrected address space.
23 static int sec_qfprom_reg_read(void *context, unsigned int reg, void *_val, size_t bytes) in sec_qfprom_reg_read() argument
31 for (i = 0; i < bytes; i++, reg++) { in sec_qfprom_reg_read()
32 if (i == 0 || reg % 4 == 0) { in sec_qfprom_reg_read()
33 if (qcom_scm_io_readl(priv->base + (reg & ~3), &read_val)) { in sec_qfprom_reg_read()
34 dev_err(priv->dev, "Couldn't access fuse register\n"); in sec_qfprom_reg_read()
35 return -EINVAL; in sec_qfprom_reg_read()
[all …]
/linux-6.14.4/drivers/mfd/
Dintel-m10-bmc-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel MAX 10 Board Management Controller chip - common code
5 * Copyright (C) 2018-2020 Intel Corporation. All rights reserved.
12 #include <linux/mfd/intel-m10-bmc.h>
18 if (!m10bmc->info->handshake_sys_reg_nranges) in m10bmc_fw_state_set()
21 down_write(&m10bmc->bmcfw_lock); in m10bmc_fw_state_set()
22 m10bmc->bmcfw_state = new_state; in m10bmc_fw_state_set()
23 up_write(&m10bmc->bmcfw_lock); in m10bmc_fw_state_set()
29 * handshake registers during a secure update.
33 if (!m10bmc->info->handshake_sys_reg_nranges) in m10bmc_reg_always_available()
[all …]
/linux-6.14.4/drivers/iommu/arm/arm-smmu/
Darm-smmu-impl.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #define pr_fmt(fmt) "arm-smmu: " fmt
10 #include "arm-smmu.h"
44 /* Since we don't care for sGFAR, we can do without 64-bit accessors */
65 cs->id_base = atomic_fetch_add(smmu->num_context_banks, &context_count); in cavium_cfg_probe()
66 dev_notice(smmu->dev, "\tenabling workaround for Cavium erratum 27704\n"); in cavium_cfg_probe()
74 struct cavium_smmu *cs = container_of(smmu_domain->smmu, in cavium_init_context()
77 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2) in cavium_init_context()
78 smmu_domain->cfg.vmid += cs->id_base; in cavium_init_context()
80 smmu_domain->cfg.asid += cs->id_base; in cavium_init_context()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/interrupt-controller/
Dmarvell,icu.txt2 --------------------------------
5 responsible for collecting all wired-interrupt sources in the CP and
8 These messages will access a different GIC memory area depending on
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
24 * "marvell,cp110-icu-sr"
25 * "marvell,cp110-icu-sei"
26 * "marvell,cp110-icu-rei"
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/timer/
Dti,timer-dm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI dual-mode timer
10 - Tony Lindgren <[email protected]>
13 The TI dual-mode timer is a general purpose timer with PWM capabilities.
18 - items:
19 - enum:
20 - ti,am335x-timer
[all …]
/linux-6.14.4/drivers/perf/
Darm_pmu_platform.c1 // SPDX-License-Identifier: GPL-2.0
30 int ret = -ENODEV; in probe_current_pmu()
34 for (; info->init != NULL; info++) { in probe_current_pmu()
35 if ((cpuid & info->mask) != info->cpuid) in probe_current_pmu()
37 ret = info->init(pmu); in probe_current_pmu()
48 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; in pmu_parse_percpu_irq()
50 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus); in pmu_parse_percpu_irq()
54 for_each_cpu(cpu, &pmu->supported_cpus) in pmu_parse_percpu_irq()
55 per_cpu(hw_events->irq, cpu) = irq; in pmu_parse_percpu_irq()
62 return of_property_present(node, "interrupt-affinity"); in pmu_has_irq_affinity()
[all …]
/linux-6.14.4/drivers/rtc/
Drtc-mxc_v2.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
21 #define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
26 #define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
29 #define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
30 #define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
31 #define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
32 #define SRTC_LPCR 0x10 /* LP Control Reg */
33 #define SRTC_LPSR 0x14 /* LP Status Reg */
34 #define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/arm/
Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <[email protected]>
11 - Will Deacon <[email protected]>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
[all …]
Darm,cci-400.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <[email protected]>
13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
30 - arm,cci-550
[all …]
/linux-6.14.4/drivers/iommu/
Dipmmu-vmsa.c1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU API for Renesas VMSA-compatible IPMMU
6 * Copyright (C) 2014-2020 Renesas Electronics Corporation
11 #include <linux/dma-mapping.h>
18 #include <linux/io-pgtable.h>
29 #include <asm/dma-iommu.h>
32 #define arm_iommu_attach_device(...) -ENODEV
37 #define IPMMU_CTX_INVALID -1
93 /* -----------------------------------------------------------------------------
100 #define IMCTR 0x0000 /* R-Car Gen2/3 */
[all …]
/linux-6.14.4/arch/xtensa/include/asm/
Dthread_info.h2 * include/asm-xtensa/thread_info.h
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
24 * low level task data that entry.S needs immediate access to
25 * - this struct should fit entirely inside of one cache line
26 * - this struct shares the supervisor stack pages
27 * - if the contents of this structure are changed, the assembly constants
51 unsigned long status; /* thread-synchronous flags */
65 * If i-th bit is set then coprocessor state is loaded into the
80 * macros/functions for gaining access to the thread information structure
105 #define GET_THREAD_INFO(reg,sp) \ argument
[all …]
/linux-6.14.4/Documentation/driver-api/
Dvfio.rst2 VFIO - "Virtual Function I/O" [1]_
7 allotted. This includes x86 hardware with AMD-Vi and Intel VT-d,
10 agnostic framework for exposing direct device access to userspace, in
11 a secure, IOMMU protected environment. In other words, this allows
12 safe [2]_, non-privileged, userspace drivers.
15 access ("device assignment") when configured for the highest possible
19 bare-metal device drivers [3]_.
22 field, also benefit from low-overhead, direct device access from
23 userspace. Examples include network adapters (often non-TCP/IP based)
28 and requires root privileges to access things like PCI configuration
[all …]
/linux-6.14.4/drivers/hwtracing/coresight/
Dcoresight-etm4x.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
13 #include "coresight-priv.h"
17 * 0x000 - 0x2FC: Trace registers
18 * 0x300 - 0x314: Management registers
19 * 0x318 - 0xEFC: Trace registers
21 * 0xFA0 - 0xFA4: Trace registers
22 * 0xFA8 - 0xFFC: Management registers
24 /* Trace registers (0x000-0x2FC) */
47 #define TRCSEQEVRn(n) (0x100 + (n * 4)) /* n = 0-2 */
[all …]
/linux-6.14.4/drivers/net/wireless/silabs/wfx/
Dfwio.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2017-2020, Silicon Laboratories, Inc.
6 * Copyright (c) 2010, ST-Ericsson
88 return -ENOMEM; in wfx_sram_write_dma_safe()
107 wdev->pdata.file_fw, keyset_chip); in get_firmware()
108 ret = firmware_request_nowarn(fw, filename, wdev->dev); in get_firmware()
110 dev_info(wdev->dev, "can't load %s, falling back to %s.sec\n", in get_firmware()
111 filename, wdev->pdata.file_fw); in get_firmware()
112 snprintf(filename, sizeof(filename), "%s.sec", wdev->pdata.file_fw); in get_firmware()
113 ret = request_firmware(fw, filename, wdev->dev); in get_firmware()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/interconnect/
Dfsl,imx8m-noc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <[email protected]>
17 ("Global Programmers View") but not all. Access to this area might be denied
18 for normal (non-secure) world.
20 The buses are based on externally licensed IPs such as ARM NIC-301 and
27 - items:
28 - enum:
[all …]
/linux-6.14.4/include/linux/mfd/
Dintel-m10-bmc.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2018-2020 Intel Corporation, Inc.
48 /* Secure update doorbell register, in system register region */
188 * struct m10bmc_csr_map - Intel MAX 10 BMC CSR register map
212 * struct intel_m10bmc_platform_info - Intel MAX 10 BMC platform specific information
230 * struct intel_m10bmc_flash_bulk_ops - device specific operations for flash R/W
233 * @lock_write: locks flash access for erase+write
234 * @unlock_write: unlock flash access
237 * is locked, @read returns -EBUSY.
254 * struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure
[all …]
/linux-6.14.4/drivers/crypto/caam/
Dregs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * CAAM hardware register-level view
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
15 #include <linux/io-64-nonatomic-hi-lo.h>
18 * Architecture-specific register access methods
20 * CAAM's bus-addressable registers are 64 bits internally.
21 * They have been wired to be safely accessible on 32-bit
24 * can be treated as two 32-bit entities, or finally (c) if they
25 * must be treated as a single 64-bit value, then this can safely
26 * be done with two 32-bit cycles.
[all …]
/linux-6.14.4/drivers/mailbox/
Dti-msgmgr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2022 Texas Instruments Incorporated - https://www.ti.com/
22 #include <linux/soc/ti/ti-msgmgr.h>
24 #define Q_DATA_OFFSET(proxy, queue, reg) \ argument
25 ((0x10000 * (proxy)) + (0x80 * (queue)) + ((reg) * 4))
30 #define SPROXY_THREAD_DATA_OFFSET(tid, reg) \ argument
31 (SPROXY_THREAD_OFFSET(tid) + ((reg) * 0x4) + 0x4)
41 * struct ti_msgmgr_valid_queue_desc - SoC valid queues meant for this processor
53 * struct ti_msgmgr_desc - Description of message manager integration
63 * @valid_queues: List of Valid queues that the processor can access
[all …]
/linux-6.14.4/arch/arm64/kvm/hyp/nvhe/
Dffa.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * FF-A v1.0 proxy to filter out invalid memory-sharing SMC calls issued by
4 * the host. FF-A is a slightly more palatable abbreviation of "Arm Firmware
5 * Framework for Arm A-profile", which is specified by Arm in document
8 * Copyright (C) 2022 - Google LLC
12 * all calls falling within the FF-A range. Each call is either:
14 * - Forwarded on unmodified to the SPMD at EL3
15 * - Rejected as "unsupported"
16 * - Accompanied by a host stage-2 page-table check/update and reissued
19 * accessible to the secure world using FF-A will be detected either here
[all …]

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