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/linux-6.14.4/Documentation/devicetree/bindings/mmc/
Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ulf Hansson <[email protected]>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
[all …]
Dmmc-controller-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <[email protected]>
14 possible slots or ports for multi-slot controllers.
17 "#address-cells":
22 "#size-cells":
29 broken-cd:
34 cd-gpios:
[all …]
Dmarvell,xenon-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 mmc-controller.yaml and the properties used by the Xenon implementation.
20 - Ulf Hansson <[email protected]>
25 - enum:
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
29 - items:
[all …]
Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adrian Hunter <[email protected]>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
[all …]
Dsprd,sdhci-r11.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/sprd,sdhci-r11.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <[email protected]>
11 - Baolin Wang <[email protected]>
12 - Chunyan Zhang <[email protected]>
16 const: sprd,sdhci-r11
27 - description: SDIO source clock
28 - description: gate clock for enabling/disabling the device
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/arm/
Dqcom-soc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/qcom-soc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <[email protected]>
15 qcom,SoC-IP
18 qcom,sdm845-llcc-bwmon
26 pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
28 - compatible
34 - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+(pro)?-.*$"
[all …]
/linux-6.14.4/arch/arm/boot/dts/st/
Dstm32mp135f-dhcor-dhsbc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG
7 * DHCOR PCB number: 718-100 or newer
8 * DHSBC PCB number: 719-100 or newer
11 /dts-v1/;
13 #include <dt-bindings/regulator/st,stm32mp13-regulator.h>
16 #include "stm32mp13xx-dhcor-som.dtsi"
20 compatible = "dh,stm32mp135f-dhcor-dhsbc",
21 "dh,stm32mp135f-dhcor-som",
32 stdout-path = "serial0:115200n8";
[all …]
/linux-6.14.4/arch/arm/boot/dts/intel/socfpga/
Dsocfpga_arria10_socdk_sdmmc.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
6 /dts-v1/;
11 cap-sd-highspeed;
12 cap-mmc-highspeed;
13 broken-cd;
14 bus-width = <4>;
15 clk-phase-sd-hs = <0>, <135>;
19 sdmmca-ecc@ff8c2c00 {
20 compatible = "altr,socfpga-sdmmc-ecc";
[all …]
Dsocfpga_arria5.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
16 clock-frequency = <25000000>;
22 broken-cd;
23 bus-width = <4>;
24 cap-mmc-highspeed;
25 cap-sd-highspeed;
26 clk-phase-sd-hs = <0>, <135>;
30 cpu1-start-addr = <0xffd080c4>;
Dsocfpga_cyclone5.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
16 clock-frequency = <25000000>;
22 broken-cd;
23 bus-width = <4>;
24 cap-mmc-highspeed;
25 cap-sd-highspeed;
26 clk-phase-sd-hs = <0>, <135>;
30 cpu1-start-addr = <0xffd080c4>;
Dsocfpga_cyclone5_mcv.dtsi1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
19 &mmc0 { /* On-SoM eMMC */
20 bus-width = <8>;
21 clk-phase-sd-hs = <0>, <135>;
Dsocfpga_arria10_mercury_aa1.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 compatible = "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,socfpga";
25 stdout-path = "serial1:115200n8";
30 phy-mode = "rgmii";
31 phy-addr = <0xffffffff>; /* probe for phy addr */
33 max-frame-size = <3800>;
35 phy-handle = <&phy3>;
38 #address-cells = <1>;
39 #size-cells = <0>;
40 compatible = "snps,dwmac-mdio";
[all …]
/linux-6.14.4/drivers/mmc/host/
Ddw_mmc-pltfm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include <linux/mfd/altera-sysmgr.h>
24 #include "dw_mmc-pltfm.h"
36 host = devm_kzalloc(&pdev->dev, sizeof(struct dw_mci), GFP_KERNEL); in dw_mci_pltfm_register()
38 return -ENOMEM; in dw_mci_pltfm_register()
40 host->irq = platform_get_irq(pdev, 0); in dw_mci_pltfm_register()
41 if (host->irq < 0) in dw_mci_pltfm_register()
42 return host->irq; in dw_mci_pltfm_register()
44 host->drv_data = drv_data; in dw_mci_pltfm_register()
45 host->dev = &pdev->dev; in dw_mci_pltfm_register()
[all …]
/linux-6.14.4/arch/arm/boot/dts/nxp/imx/
Dimx6dl-dhcom-picoitx.dts1 // SPDX-License-Identifier: GPL-2.0+
6 * DHCM-iMX6DL-C080-R102-F0819-E-SD-RTC-T-HS-I-01D2
7 * DHCOM PCB number: 493-300 or newer
8 * PicoITX PCB number: 487-600 or newer
10 /dts-v1/;
13 #include "imx6qdl-dhcom-som.dtsi"
14 #include "imx6qdl-dhcom-picoitx.dtsi"
18 compatible = "dh,imx6dl-dhcom-picoitx", "dh,imx6dl-dhcom-som",
Dimx6dl-dhcom-pdk2.dts1 // SPDX-License-Identifier: GPL-2.0+
6 * DHCM-iMX6DL-C080-R102-F0819-E-SD-RTC-T-HS-I-01D2
7 * DHCOM PCB number: 493-400 or newer
8 * PDK2 PCB number: 516-400 or newer
10 /dts-v1/;
13 #include "imx6qdl-dhcom-som.dtsi"
14 #include "imx6qdl-dhcom-pdk2.dtsi"
18 compatible = "dh,imx6dl-dhcom-pdk2", "dh,imx6dl-dhcom-som",
Dimx6q-dhcom-pdk2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2021 DH electronics GmbH
7 * DHCM-iMX6Q-C080-R102-F0819-E-SD-RTC-T-HS-I-01D2
8 * DHCOM PCB number: 493-300 or newer
9 * PDK2 PCB number: 516-400 or newer
11 /dts-v1/;
14 #include "imx6qdl-dhcom-som.dtsi"
15 #include "imx6qdl-dhcom-pdk2.dtsi"
19 compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som",
/linux-6.14.4/drivers/media/i2c/
Dtw9910.c1 // SPDX-License-Identifier: GPL-2.0
13 * Copyright 2006-7 Jonathan Corbet <[email protected]>
26 #include <linux/v4l2-mediabus.h>
30 #include <media/v4l2-subdev.h>
136 #define IFSEL_S 0x10 /* 01 : S-video decoding */
146 /* 1 : ITU-R-656 compatible data sequence format */
147 #define LEN 0x40 /* 0 : 8-bit YCrCb 4:2:2 output format */
148 /* 1 : 16-bit YCrCb 4:2:2 output format.*/
150 /* 0 : free-run output mode */
151 #define AINC 0x10 /* Serial interface auto-indexing control */
[all …]
/linux-6.14.4/Documentation/arch/arm/stm32/
Dstm32h750-overview.rst6 ------------
8 The STM32H750 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @480MHz
12 - 128K internal flash, 1MBytes internal RAM
13 - FMC controller to connect SDRAM, NOR and NAND memories
14 - Dual mode QSPI
15 - SD/MMC/SDIO support
16 - Ethernet controller
17 - USB OTFG FS & HS controllers
18 - I2C, SPI, CAN busses support
[all …]
Dstm32h743-overview.rst6 ------------
8 The STM32H743 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @400MHz
12 - 2MB internal flash, 1MBytes internal RAM
13 - FMC controller to connect SDRAM, NOR and NAND memories
14 - Dual mode QSPI
15 - SD/MMC/SDIO support
16 - Ethernet controller
17 - USB OTFG FS & HS controllers
18 - I2C, SPI, CAN busses support
[all …]
Dstm32f746-overview.rst6 ------------
8 The STM32F746 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @216MHz
12 - 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM)
13 - FMC controller to connect SDRAM, NOR and NAND memories
14 - Dual mode QSPI
15 - SD/MMC/SDIO support
16 - Ethernet controller
17 - USB OTFG FS & HS controllers
18 - I2C, SPI, CAN busses support
[all …]
Dstm32f769-overview.rst6 ------------
8 The STM32F769 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @216MHz
12 - 2MB internal flash, 512KBytes internal RAM (+4KB of backup SRAM)
13 - FMC controller to connect SDRAM, NOR and NAND memories
14 - Dual mode QSPI
15 - SD/MMC/SDIO support*2
16 - Ethernet controller
17 - USB OTFG FS & HS controllers
18 - I2C*4, SPI*6, CAN*3 busses support
[all …]
/linux-6.14.4/arch/arm64/boot/dts/intel/
Dsocfpga_n5x_socdk.dts1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "intel,n5x-socdk", "intel,socfpga-agilex";
19 stdout-path = "serial0:115200n8";
29 sdram_edac: memory-controller@f87f8000 {
30 compatible = "snps,ddrc-3.80a";
38 compatible = "intel,easic-n5x-clkmgr";
43 phy-mode = "rgmii";
44 phy-handle = <&phy0>;
46 max-frame-size = <9000>;
49 #address-cells = <1>;
[all …]
Dsocfpga_agilex_socdk.dts1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
19 stdout-path = "serial0:115200n8";
23 compatible = "gpio-leds";
53 phy-mode = "rgmii";
54 phy-handle = <&phy0>;
56 max-frame-size = <9000>;
59 #address-cells = <1>;
60 #size-cells = <0>;
61 compatible = "snps,dwmac-mdio";
[all …]
/linux-6.14.4/arch/arm/boot/dts/aspeed/
Daspeed-ast2600-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/gpio/aspeed-gpio.h>
11 compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
26 reserved-memory {
27 #address-cells = <1>;
28 #size-cells = <1>;
34 compatible = "shared-dma-pool";
41 compatible = "shared-dma-pool";
[all …]
/linux-6.14.4/arch/arm64/boot/dts/freescale/
Dimx8mp-dhcom-picoitx.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2023-2024 Marek Vasut <[email protected]>
6 * DHCM-iMX8ML8-C160-R204-F1638-SPI16-E-SD-RTC-T-RGB-I-01D2
7 * DHCOM PCB number: 660-200 or newer
8 * PicoITX PCB number: 487-600 or newer
11 /dts-v1/;
13 #include <dt-bindings/leds/common.h>
14 #include "imx8mp-dhcom-som.dtsi"
18 compatible = "dh,imx8mp-dhcom-picoitx", "dh,imx8mp-dhcom-som",
22 stdout-path = &uart1;
[all …]

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