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/linux-6.14.4/Documentation/devicetree/bindings/display/msm/
Dqcom,sc7280-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SC7280 Display MDSS
10 - Krishna Manikandan <[email protected]>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS are mentioned for SC7280.
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sc7280-mdss
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Ddp-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuogee Hsieh <[email protected]>
11 - Abhinav Kumar <[email protected]>
20 - enum:
21 - qcom,sa8775p-dp
22 - qcom,sc7180-dp
23 - qcom,sc7280-dp
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/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dqcom,sc7280-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7280-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on SC7280
10 - Taniya Das <[email protected]>
14 domains on SC7280.
16 See also:: include/dt-bindings/clock/qcom,dispcc-sc7280.h
20 const: qcom,sc7280-dispcc
24 - description: Board XO source
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/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dsc7280-herobrine-crd.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sc7280 CRD 3+ board device tree source
8 /dts-v1/;
10 #include "sc7280-herobrine.dtsi"
11 #include "sc7280-herobrine-audio-wcd9385.dtsi"
12 #include "sc7280-herobrine-lte-sku.dtsi"
15 model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)";
16 compatible = "google,zoglin", "google,hoglin", "qcom,sc7280";
27 vreg_edp_bl_crd: vreg-edp-bl-crd-regulator {
28 compatible = "regulator-fixed";
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Dsc7280-herobrine-herobrine-r1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "sc7280-herobrine.dtsi"
11 #include "sc7280-herobrine-audio-rt5682.dtsi"
12 #include "sc7280-herobrine-lte-sku.dtsi"
16 compatible = "google,herobrine", "qcom,sc7280";
59 clock-frequency = <400000>;
64 pinctrl-names = "default";
65 pinctrl-0 = <&tp_int_odl>;
67 interrupt-parent = <&tlmm>;
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Dsc7280-qcard.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sc7280 Qcard device tree source
5 * Qcard PCB has the processor, RAM, eMMC (if stuffed), and eDP connector (if
14 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
15 #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
16 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
17 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
19 #include "sc7280.dtsi"
34 wcd9385: audio-codec-1 {
35 compatible = "qcom,wcd9385-codec";
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Dsc7280-herobrine.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
16 #include <dt-bindings/input/gpio-keys.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/leds/common.h>
20 #include "sc7280-qcard.dtsi"
21 #include "sc7280-chrome-common.dtsi"
25 stdout-path = "serial0:115200n8";
38 ppvar_sys: ppvar-sys-regulator {
39 compatible = "regulator-fixed";
40 regulator-name = "ppvar_sys";
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Dsc7280.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * sc7280 SoC device tree source
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
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Dqcs8300.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
9 #include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
10 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
11 #include <dt-bindings/clock/qcom,sa8775p-videocc.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
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Dsa8775p.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/interconnect/qcom,icc.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
11 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
12 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h>
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/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dqcom,edp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/qcom,edp-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm eDP PHY
11 - Bjorn Andersson <[email protected]>
14 The Qualcomm eDP PHY is found in a number of Qualcomm platform and provides
20 - qcom,sa8775p-edp-phy
21 - qcom,sc7280-edp-phy
22 - qcom,sc8180x-edp-phy
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/linux-6.14.4/drivers/phy/qualcomm/
Dphy-qcom-edp.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
17 #include <linux/phy/phy-dp.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp-dp-phy.h"
26 #include "phy-qcom-qmp-qserdes-com-v4.h"
27 #include "phy-qcom-qmp-qserdes-com-v6.h"
76 int (*com_power_on)(const struct qcom_edp *edp);
77 int (*com_resetsm_cntrl)(const struct qcom_edp *edp);
78 int (*com_bias_en_clkbuflr)(const struct qcom_edp *edp);
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/linux-6.14.4/drivers/gpu/drm/msm/dp/
Ddp_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
32 MODULE_PARM_DESC(psr_enabled, "enable PSR for eDP and DP displays");
173 { .compatible = "qcom,sa8775p-dp", .data = &msm_dp_desc_sa8775p },
174 { .compatible = "qcom,sc7180-dp", .data = &msm_dp_desc_sc7180 },
175 { .compatible = "qcom,sc7280-dp", .data = &msm_dp_desc_sc7280 },
176 { .compatible = "qcom,sc7280-edp", .data = &msm_dp_desc_sc7280 },
177 { .compatible = "qcom,sc8180x-dp", .data = &msm_dp_desc_sc8180x },
178 { .compatible = "qcom,sc8180x-edp", .data = &msm_dp_desc_sc8180x },
179 { .compatible = "qcom,sc8280xp-dp", .data = &msm_dp_desc_sc8280xp },
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/linux-6.14.4/drivers/gpu/drm/msm/
Dmsm_mdss.c2 * SPDX-License-Identifier: GPL-2.0
52 path0 = devm_of_icc_get(dev, "mdp0-mem"); in msm_mdss_parse_data_bus_icc_path()
56 msm_mdss->mdp_path[0] = path0; in msm_mdss_parse_data_bus_icc_path()
57 msm_mdss->num_mdp_paths = 1; in msm_mdss_parse_data_bus_icc_path()
59 path1 = devm_of_icc_get(dev, "mdp1-mem"); in msm_mdss_parse_data_bus_icc_path()
61 msm_mdss->mdp_path[1] = path1; in msm_mdss_parse_data_bus_icc_path()
62 msm_mdss->num_mdp_paths++; in msm_mdss_parse_data_bus_icc_path()
65 reg_bus_path = of_icc_get(dev, "cpu-cfg"); in msm_mdss_parse_data_bus_icc_path()
67 msm_mdss->reg_bus_path = reg_bus_path; in msm_mdss_parse_data_bus_icc_path()
80 interrupts = readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_INTR_STATUS); in msm_mdss_irq()
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/linux-6.14.4/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-[email protected]
88 F: drivers/scsi/3w-*
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