| /linux-6.14.4/drivers/platform/mellanox/ |
| D | mlxbf-tmfifo.c | 1 // SPDX-License-Identifier: GPL-2.0+
24 #include "mlxbf-tmfifo-regs.h"
26 /* Vring size. */
29 /* Console Tx buffer size. */
35 /* House-keeping timer interval. */
38 /* Virtual devices sharing the TM FIFO. */
53 /* ACPI UID for BlueField-3. */
59 * struct mlxbf_tmfifo_vring - Structure of the TmFifo virtual ring
71 * @num: vring size (number of descriptors)
72 * @align: vring alignment size
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| /linux-6.14.4/Documentation/devicetree/bindings/net/ |
| D | ibm,emac.txt | 8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
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| D | altr,tse.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Maxime Chevallier <[email protected]>
15 - const: altr,tse-1.0
16 - const: ALTR,tse-1.0
18 - const: altr,tse-msgdma-1.0
23 interrupt-names:
25 - const: rx_irq
26 - const: tx_irq
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| D | ethernet-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <[email protected]>
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
31 local-mac-address property.
32 $ref: /schemas/types.yaml#/definitions/uint8-array
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| /linux-6.14.4/arch/powerpc/boot/dts/ |
| D | mpc5121.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2007-2008 Freescale Semiconductor Inc.
8 #include <dt-bindings/clock/mpc512x-clock.h>
10 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&ipic>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <0x20>; /* 32 bytes */
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| D | eiger.dts | 11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
40 d-cache-line-size = <32>;
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| D | arches.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
17 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
24 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by U-Boot */
42 timebase-frequency = <0>; /* Filled in by U-Boot */
43 i-cache-line-size = <32>;
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| D | glacier.dts | 4 * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <[email protected]>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
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| /linux-6.14.4/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpc5121-psc.txt | 4 ----------------
7 are specified by fsl,mpc5121-psc-uart nodes in the
8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is required there:
11 fsl,mpc512x-psc-uart nodes
12 --------------------------
15 - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
17 - reg : Offset and length of the register set for the PSC device
18 - interrupts : <a b> where a is the interrupt number of the
19 PSC FIFO Controller and b is a field that represents an
[all …]
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| /linux-6.14.4/arch/arm/boot/dts/microchip/ |
| D | sam9x7.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family
10 #include <dt-bindings/clock/at91.h>
11 #include <dt-bindings/dma/at91.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/mfd/at91-usart.h>
16 #include <dt-bindings/mfd/atmel-flexcom.h>
17 #include <dt-bindings/pinctrl/at91.h>
[all …]
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| D | sam9x60.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
10 #include <dt-bindings/dma/at91.h>
11 #include <dt-bindings/pinctrl/at91.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/clock/at91.h>
15 #include <dt-bindings/mfd/at91-usart.h>
16 #include <dt-bindings/mfd/atmel-flexcom.h>
19 #address-cells = <1>;
[all …]
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| D | sama5d2.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
9 #include <dt-bindings/dma/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/mfd/at91-usart.h>
13 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
20 interrupt-parent = <&aic>;
[all …]
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| D | lan966x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mfd/atmel-flexcom.h>
14 #include <dt-bindings/dma/at91.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/clock/microchip,lan966x.h>
21 interrupt-parent = <&gic>;
22 #address-cells = <1>;
[all …]
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| /linux-6.14.4/drivers/net/ethernet/intel/fm10k/ |
| D | fm10k_mbx.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2019 Intel Corporation. */
7 * fm10k_fifo_init - Initialize a message FIFO
8 * @fifo: pointer to FIFO
9 * @buffer: pointer to memory to be used to store FIFO
10 * @size: maximum message size to store in FIFO, must be 2^n - 1
12 static void fm10k_fifo_init(struct fm10k_mbx_fifo *fifo, u32 *buffer, u16 size) in fm10k_fifo_init() argument
14 fifo->buffer = buffer; in fm10k_fifo_init()
15 fifo->size = size; in fm10k_fifo_init()
16 fifo->head = 0; in fm10k_fifo_init()
[all …]
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| /linux-6.14.4/drivers/net/ethernet/sun/ |
| D | sunqe.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
14 #define GLOB_PSIZE 0x08UL /* Packet Size */
15 #define GLOB_MSIZE 0x0cUL /* Local-memory Size */
16 #define GLOB_RSIZE 0x10UL /* Receive partition size */
17 #define GLOB_TSIZE 0x14UL /* Transmit partition size */
34 #define GLOB_PSIZE_2048 0x00 /* 2k packet size */
35 #define GLOB_PSIZE_4096 0x01 /* 4k packet size */
36 #define GLOB_PSIZE_6144 0x10 /* 6k packet size */
37 #define GLOB_PSIZE_8192 0x11 /* 8k packet size */
45 /* The following registers are for per-qe channel information/status. */
[all …]
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| D | cassini.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
42 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
45 * DEFAULT: 0x0, SIZE: 5 bits
54 /* if enabled, BIM can send bursts across PCI bus > cacheline size. burst
57 * DEFAULT: 0x0, SIZE: 1 bit
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
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| D | sungem.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define GREG_SEBSTATE_RXWON 0x00000004 /* RX won internal arbitration */
31 #define GREG_CFG_RXDMALIM 0x000007c0 /* RX DMA grant limit */
34 #define GREG_CFG_ENBUG2FIX 0x00001000 /* Fix Rx hang after overflow */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
48 #define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */
49 #define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */
50 #define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */
53 #define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */
69 * signalled to the cpu. GREG_IACK can be used to clear specific top-level
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/spi/ |
| D | spi-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <[email protected]>
20 pattern: "^spi(@.*|-([0-9]|[1-9][0-9]+))?$"
22 "#address-cells":
25 "#size-cells":
28 cs-gpios:
32 increased automatically with max(cs-gpios, hardware chip selects).
[all …]
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| /linux-6.14.4/arch/m68k/include/asm/ |
| D | m54xxpci.h | 4 * m54xxpci.h -- ColdFire 547x and 548x PCI bus support
45 #define PCITPSR (CONFIG_MBAR + 0x8400) /* TX packet size */
53 #define PCITFDR (CONFIG_MBAR + 0x8440) /* TX FIFO data */
54 #define PCITFSR (CONFIG_MBAR + 0x8444) /* TX FIFO status */
55 #define PCITFCR (CONFIG_MBAR + 0x8448) /* TX FIFO control */
56 #define PCITFAR (CONFIG_MBAR + 0x844c) /* TX FIFO alarm */
57 #define PCITFRPR (CONFIG_MBAR + 0x8450) /* TX FIFO read pointer */
58 #define PCITFWPR (CONFIG_MBAR + 0x8454) /* TX FIFO write pointer */
60 #define PCIRPSR (CONFIG_MBAR + 0x8480) /* RX packet size */
61 #define PCIRSAR (CONFIG_MBAR + 0x8484) /* RX start address */
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| /linux-6.14.4/drivers/net/can/spi/mcp251xfd/ |
| D | mcp251xfd-ram.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
6 // Marc Kleine-Budde <[email protected]>
9 #include "mcp251xfd-ram.h"
17 max = min_t(u8, obj->max, obj->fifo_num * config->fifo_depth); in can_ram_clamp()
18 return clamp(val, obj->min, max); in can_ram_clamp()
26 u8 fifo_num = obj->fifo_num; in can_ram_rounddown_pow_of_two()
32 /* Use 1st FIFO for coalescing, if requested. in can_ram_rounddown_pow_of_two()
34 * Either use complete FIFO (and FIFO Full IRQ) for in can_ram_rounddown_pow_of_two()
35 * coalescing or only half of FIFO (FIFO Half Full in can_ram_rounddown_pow_of_two()
[all …]
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| D | mcp251xfd-ring.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
6 // Marc Kleine-Budde <[email protected]>
18 #include "mcp251xfd-ram.h"
31 len = last_byte - first_byte + 1; in mcp251xfd_cmd_prepare_write_reg()
37 if (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG)) { in mcp251xfd_cmd_prepare_write_reg()
38 len += sizeof(write_reg_buf->nocrc.cmd); in mcp251xfd_cmd_prepare_write_reg()
43 len += sizeof(write_reg_buf->safe.cmd); in mcp251xfd_cmd_prepare_write_reg()
44 crc = mcp251xfd_crc16_compute(&write_reg_buf->safe, len); in mcp251xfd_cmd_prepare_write_reg()
48 len += sizeof(write_reg_buf->safe.crc); in mcp251xfd_cmd_prepare_write_reg()
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/mmc/ |
| D | synopsys-dw-mshc-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: mmc-controller.yaml#
13 - Ulf Hansson <[email protected]>
20 reset-names:
23 clock-frequency:
29 fifo-depth:
31 The maximum size of the tx/rx fifo's. If this property is not
[all …]
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| /linux-6.14.4/drivers/spi/ |
| D | spi-zynq-qspi.c | 1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/spi/spi-mem.h>
28 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */
29 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */
30 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */
31 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */
34 #define ZYNQ_QSPI_TX_THRESH_OFFSET 0x28 /* TX FIFO Watermark Reg, RW */
35 #define ZYNQ_QSPI_RX_THRESH_OFFSET 0x2C /* RX FIFO Watermark Reg, RW */
53 #define ZYNQ_QSPI_CONFIG_FWIDTH_MASK GENMASK(7, 6) /* FIFO width */
57 * QSPI Configuration Register - Baud rate and target select
[all …]
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| /linux-6.14.4/drivers/net/ethernet/oki-semi/pch_gbe/ |
| D | pch_gbe.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 1999 - 2010 Intel Corporation.
26 * pch_gbe_regs_mac_adr - Structure holding values of mac address registers
35 * pch_udc_regs - Structure holding values of MAC registers
96 #define PCH_GBE_INT_RX_FIFO_ERR 0x00000008 /* Receive FIFO Overflow */
101 #define PCH_GBE_INT_TX_FIFO_ERR 0x00000400 /* Transmission FIFO underflow. */
118 #define PCH_GBE_TX_RST 0x00008000 /* TX MAC, TX FIFO, TX DMA reset */
119 #define PCH_GBE_RX_RST 0x00004000 /* RX MAC, RX FIFO, RX DMA reset */
123 #define PCH_GBE_RX_TCPIPACC_OFF 0x00000004 /* RX TCP/IP ACC Disabled */
125 #define PCH_GBE_RX_TCPIPACC_EN 0x00000001 /* RX TCP/IP ACC Enable */
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| /linux-6.14.4/Documentation/devicetree/bindings/usb/ |
| D | snps,dwc3-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <[email protected]>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
28 $ref: usb-xhci.yaml#
[all …]
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