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/linux-6.14.4/Documentation/devicetree/bindings/net/dsa/
Dnxp,sja1105.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at
16 - Vladimir Oltean <[email protected]>
21 - nxp,sja1105e
22 - nxp,sja1105t
23 - nxp,sja1105p
24 - nxp,sja1105q
25 - nxp,sja1105r
[all …]
Dvitesse,vsc73xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <[email protected]>
13 The Vitesse DSA Switches were produced in the early-to-mid 2000s.
19 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
20 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
21 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
22 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
27 reside inside a SPI bus device tree node, see spi/spi-bus.txt
[all …]
Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - [email protected]
13 - $ref: dsa.yaml#/$defs/ethernet-ports
18 - microchip,lan9370
19 - microchip,lan9371
20 - microchip,lan9372
21 - microchip,lan9373
22 - microchip,lan9374
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dmicrel-ksz90x1.txt4 to clock delays. You can specify clock delay values in the PHY OF
8 Note that these settings are applied after any phy-specific fixup from
15 value is 0, the maximum value is 3000, and it can be specified in 200ps
17 skew values actually increase in 120ps steps, starting from -840ps. The
23 The following table shows the actual skew delay you will get for each of the
27 Device Tree Value Delay Pad Skew Register Value
28 -----------------------------------------------------
29 0 -840ps 0000
30 200 -720ps 0001
31 400 -600ps 0010
[all …]
Drenesas,etheravb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergei Shtylyov <[email protected]>
15 - items:
16 - enum:
17 - renesas,etheravb-r8a7742 # RZ/G1H
18 - renesas,etheravb-r8a7743 # RZ/G1M
19 - renesas,etheravb-r8a7744 # RZ/G1N
20 - renesas,etheravb-r8a7745 # RZ/G1E
[all …]
Damlogic,meson-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <[email protected]>
12 - Martin Blumenstingl <[email protected]>
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
[all …]
Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <[email protected]>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
[all …]
Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <[email protected]>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
Dapm-xgene-enet.txt1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
[all …]
Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
[all …]
Drenesas,ethertsn.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Ethernet TSN End-station
10 - Niklas Söderlund <[email protected]>
14 Gbps full-duplex link via MII/GMII/RMII/RGMII. Depending on the connected PHY.
17 - $ref: ethernet-controller.yaml#
22 - enum:
23 - renesas,r8a779g0-ethertsn # R-Car V4H
24 - const: renesas,rcar-gen4-ethertsn
[all …]
Dti,dp83822.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <[email protected]>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
24 - $ref: ethernet-phy.yaml#
30 ti,link-loss-low:
39 ti,fiber-mode:
[all …]
Dallwinner,sun8i-a83t-emac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <[email protected]>
11 - Maxime Ripard <[email protected]>
16 - const: allwinner,sun8i-a83t-emac
17 - const: allwinner,sun8i-h3-emac
18 - const: allwinner,sun8i-r40-gmac
19 - const: allwinner,sun8i-v3s-emac
[all …]
Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <[email protected]>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
[all …]
Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <[email protected]>
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
31 local-mac-address property.
32 $ref: /schemas/types.yaml#/definitions/uint8-array
[all …]
Dingenic,mac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - 周琰杰 (Zhou Yanjie) <[email protected]>
18 - ingenic,jz4775-mac
19 - ingenic,x1000-mac
20 - ingenic,x1600-mac
21 - ingenic,x1830-mac
22 - ingenic,x2000-mac
30 interrupt-names:
[all …]
Dmicrochip,sparx5-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <[email protected]>
11 - Lars Povlsen <[email protected]>
12 - Daniel Machon <[email protected]>
15 The SparX-5 Enterprise Ethernet switch family provides a rich set of
16 Enterprise switching features such as advanced TCAM-based VLAN and
18 security through TCAM-based frame processing using versatile content
[all …]
/linux-6.14.4/arch/riscv/boot/dts/starfive/
Djh7110-starfive-visionfive-2-v1.3b.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-starfive-visionfive-2.dtsi"
12 compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
16 starfive,tx-use-rgmii-clk;
17 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
18 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
22 starfive,tx-use-rgmii-clk;
23 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
24 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
[all …]
Djh7110-pine64-star64.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
18 starfive,tx-use-rgmii-clk;
19 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
20 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
25 phy-handle = <&phy1>;
26 phy-mode = "rgmii-id";
27 starfive,tx-use-rgmii-clk;
28 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
[all …]
Djh7110-milkv-mars.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
10 model = "Milk-V Mars";
15 starfive,tx-use-rgmii-clk;
16 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
17 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
34 motorcomm,tx-clk-adj-enabled;
35 motorcomm,tx-clk-10-inverted;
36 motorcomm,tx-clk-100-inverted;
[all …]
Djh7110-starfive-visionfive-2-v1.2a.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-starfive-visionfive-2.dtsi"
12 compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
16 phy-mode = "rmii";
17 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>,
19 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>,
24 rx-internal-delay-ps = <1900>;
25 tx-internal-delay-ps = <1350>;
Djh7100-starfive-visionfive-v1.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7100-common.dtsi"
12 compatible = "starfive,visionfive-v1", "starfive,jh7100";
14 gpio-restart {
15 compatible = "gpio-restart";
22 phy-handle = <&phy>;
26 * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
27 * manual adjustment of the RX internal delay to work properly. The default
28 * RX delay provided by the driver (1.95ns) is too high, but applying a 50%
[all …]
/linux-6.14.4/drivers/net/ethernet/microchip/sparx5/lan969x/
Dlan969x_rgmii.c1 // SPDX-License-Identifier: GPL-2.0+
19 /* Clock delay selectors */
32 #define RGMII_PORT_IDX(port) ((port)->portno - LAN969X_RGMII_PORT_START_IDX)
50 /* Get the clock delay selector based on the clock delay in picoseconds. */
78 dev_err(port->sparx5->dev, "Invalid RGMII delay: %u", delay_ps); in lan969x_rgmii_get_clk_delay_sel()
79 return -EINVAL; in lan969x_rgmii_get_clk_delay_sel()
89 u32 clk_sel = lan969x_rgmii_get_clk_sel(conf->speed); in lan969x_rgmii_tx_clk_config()
101 port->sparx5, HSIO_WRAP_RGMII_CFG(idx)); in lan969x_rgmii_tx_clk_config()
110 speed_sel = lan969x_rgmii_get_speed_sel(conf->speed); in lan969x_rgmii_port_device_config()
112 etype = (port->vlan_type == SPX5_VLAN_PORT_TYPE_S_CUSTOM ? in lan969x_rgmii_port_device_config()
[all …]
/linux-6.14.4/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
35 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
56 * input RX rising/falling edge and sent to the Ethernet internals. This sets
57 * the automatically delay and skew automatically (internally).
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
62 * delay (= the counter value) when to start sampling RXEN and RXD[3:0].
66 * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1,
67 * ...) can be configured to be 1 to compensate for a delay of about 1ns.
73 /* Defined for adding a delay to the input RX_CLK for better timing.
[all …]
/linux-6.14.4/arch/arm64/boot/dts/allwinner/
Dsun50i-h6-orangepi-one-plus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 #include "sun50i-h6-orangepi.dtsi"
9 compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6";
15 reg_gmac_3v3: gmac-3v3 {
16 compatible = "regulator-fixed";
17 regulator-name = "vcc-gmac-3v3";
18 regulator-min-microvolt = <3300000>;
19 regulator-max-microvolt = <3300000>;
20 startup-delay-us = <100000>;
21 enable-active-high;
[all …]

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