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/linux-6.14.4/Documentation/devicetree/bindings/mtd/
Dqcom,nandc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <[email protected]>
15 - qcom,ipq806x-nand
16 - qcom,ipq4019-nand
17 - qcom,ipq6018-nand
18 - qcom,ipq8074-nand
19 - qcom,sdx55-nand
26 - description: Core Clock
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/linux-6.14.4/drivers/soc/qcom/
Dqcom_gsbi.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <dt-bindings/soc/qcom,gsbi.h>
83 { /* ADM 0 - B */
88 { /* ADM 0 - B */
93 { /* ADM 1 - A */
98 { /* ADM 1 - B */
113 u32 crci; member
118 { .compatible = "qcom,tcsr-ipq8064", .data = &config_ipq8064},
119 { .compatible = "qcom,tcsr-apq8064", .data = &config_apq8064},
120 { .compatible = "qcom,tcsr-msm8960", .data = &config_msm8960},
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/linux-6.14.4/drivers/mmc/host/
Dmmci_qcom_dml.c1 // SPDX-License-Identifier: GPL-2.0-only
51 void __iomem *base = host->base + DML_OFFSET; in qcom_dma_start()
52 struct mmc_data *data = host->data; in qcom_dma_start()
58 if (data->flags & MMC_DATA_READ) { in qcom_dma_start()
60 /* Set producer CRCI-x and disable consumer CRCI */ in qcom_dma_start()
67 writel_relaxed(data->blksz, base + DML_PRODUCER_BAM_BLOCK_SIZE); in qcom_dma_start()
70 writel_relaxed(data->blocks * data->blksz, in qcom_dma_start()
80 /* Set consumer CRCI-x and disable producer CRCI*/ in qcom_dma_start()
103 index = of_property_match_string(np, "dma-names", name); in of_get_dml_pipe_index()
106 return -ENODEV; in of_get_dml_pipe_index()
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/linux-6.14.4/Documentation/devicetree/bindings/serial/
Dqcom,msm-uartdm.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/serial/qcom,msm-uartdm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <[email protected]>
11 - Bjorn Andersson <[email protected]>
12 - Krzysztof Kozlowski <[email protected]>
15 The MSM serial UARTDM hardware is designed for high-speed use cases where the
16 transmit and/or receive channels can be offloaded to a dma-engine. From a
28 - enum:
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/linux-6.14.4/drivers/tty/serial/
Dmsm_serial.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/dma-mapping.h>
169 } rx; member
198 writel_relaxed(val, port->membase + off); in msm_write()
204 return readl_relaxed(port->membase + off); in msm_read()
216 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxo()
228 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxoby4()
239 if (msm_port->is_uartdm) in msm_serial_set_mnd_regs()
242 if (port->uartclk == 19200000) in msm_serial_set_mnd_regs()
244 else if (port->uartclk == 4800000) in msm_serial_set_mnd_regs()
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/linux-6.14.4/include/linux/mtd/
Dnand-qpic-common.h1 /* SPDX-License-Identifier: GPL-2.0 */
196 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
199 #define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
203 ((chip)->reg_read_dma + \
204 ((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf))
233 * @bam_ce - the array of BAM command elements
234 * @cmd_sgl - sgl for NAND BAM command pipe
235 * @data_sgl - sgl for NAND BAM consumer/producer pipe
236 * @last_data_desc - last DMA desc in data channel (tx/rx).
237 * @last_cmd_desc - last DMA desc in command channel.
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/linux-6.14.4/drivers/mtd/nand/
Dqpic_common.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
16 #include <linux/mtd/nand-qpic-common.h>
19 * qcom_free_bam_transaction() - Frees the BAM transaction memory
26 struct bam_transaction *bam_txn = nandc->bam_txn; in qcom_free_bam_transaction()
33 * qcom_alloc_bam_transaction() - allocate BAM transaction
43 unsigned int num_cw = nandc->max_cwperpage; in qcom_alloc_bam_transaction()
48 ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) + in qcom_alloc_bam_transaction()
49 (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) + in qcom_alloc_bam_transaction()
50 (sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL)); in qcom_alloc_bam_transaction()
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/linux-6.14.4/arch/arm/boot/dts/qcom/
Dqcom-ipq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11 #include <dt-bindings/soc/qcom,gsbi.h>
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