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Searched +full:rmii +full:- +full:refclk +full:- +full:in (Results 1 – 14 of 14) sorted by relevance

/linux-6.14.4/Documentation/devicetree/bindings/net/
Dnxp,tja11xx.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <[email protected]>
11 - Florian Fainelli <[email protected]>
12 - Heiner Kallweit <[email protected]>
20 - ethernet-phy-id0180.dc40
21 - ethernet-phy-id0180.dc41
22 - ethernet-phy-id0180.dc48
23 - ethernet-phy-id0180.dd00
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/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dti,phy-gmii-sel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <[email protected]>
15 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
17 (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and
18 bit fields placement in SCM are different between SoCs while fields meaning
20 +--------------+
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/linux-6.14.4/arch/arm/boot/dts/nxp/imx/
Dimx6q-bosch-acc.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Support for the i.MX6-based Bosch ACC board.
8 * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker <[email protected]>
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/leds/common.h>
20 compatible = "bosch,imx6q-acc", "fsl,imx6q";
37 backlight_lvds: backlight-lvds {
38 compatible = "pwm-backlight";
40 brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>;
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Dimx6qdl-zii-rdu2.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2016-2017 Zodiac Inflight Innovations
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/sound/fsl-imx-audmux.h>
11 stdout-path = &uart1;
15 mdio-gpio0 = &mdio1;
20 compatible = "virtual,mdio-gpio";
21 #address-cells = <1>;
22 #size-cells = <0>;
23 pinctrl-names = "default";
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/linux-6.14.4/arch/arm64/boot/dts/freescale/
Dimx8mq-zii-ultra.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 mdio-gpio0 = &mdio0;
15 stdout-path = &uart1;
19 compatible = "virtual,mdio-gpio";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_mdio_bitbang>, <&pinctrl_fec1_phy_reset>;
24 #address-cells = <1>;
25 #size-cells = <0>;
27 phy0: ethernet-phy@0 {
29 reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
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Dimx8x-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
8 stdout-path = &lpuart3;
11 colibri_gpio_keys: gpio-keys {
12 compatible = "gpio-keys";
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_gpiokeys>;
17 key-wakeup {
18 debounce-interval = <10>;
20 label = "Wake-Up";
22 wakeup-source;
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/linux-6.14.4/drivers/net/phy/
Dnxp-tja11xx.c1 // SPDX-License-Identifier: GPL-2.0
81 /* Configure REF_CLK as input in RMII mode */
205 if (phydev->link) in tja11xx_config_aneg_cable_test()
208 if (!phydev->drv->cable_test_start || in tja11xx_config_aneg_cable_test()
209 !phydev->drv->cable_test_get_status) in tja11xx_config_aneg_cable_test()
216 ret = phydev->drv->cable_test_start(phydev); in tja11xx_config_aneg_cable_test()
223 ret = phydev->drv->cable_test_get_status(phydev, &finished); in tja11xx_config_aneg_cable_test()
238 switch (phydev->master_slave_set) { in tja11xx_config_aneg()
249 return -ENOTSUPP; in tja11xx_config_aneg()
266 struct tja11xx_priv *priv = phydev->priv; in tja11xx_get_interface_mode()
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Dnxp-c45-tja11xx.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2021-2023 NXP
4 * Author: Radu Pirea <radu-[email protected]>
20 #include "nxp-c45-tja11xx.h"
195 #define NXP_C45_SKB_CB(skb) ((struct nxp_c45_skb_cb *)(skb)->cb)
300 return phydev->drv->driver_data; in nxp_c45_get_data()
308 return phy_data->regmap; in nxp_c45_get_regmap()
317 if (reg_field->size == 0) { in nxp_c45_read_reg_field()
319 return -EINVAL; in nxp_c45_read_reg_field()
322 ret = phy_read_mmd(phydev, reg_field->devad, reg_field->reg); in nxp_c45_read_reg_field()
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/linux-6.14.4/drivers/clk/
Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
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/linux-6.14.4/arch/arm64/boot/dts/rockchip/
Drk3308.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/rk3308-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
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Drk3399-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
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/linux-6.14.4/arch/mips/boot/dts/img/
Dpistachio.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/pistachio-clk.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #include <dt-bindings/reset/pistachio-resets.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
22 #address-cells = <1>;
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/linux-6.14.4/drivers/net/ethernet/cadence/
Dmacb_main.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2006 Atmel Corporation
10 #include <linux/clk-provider.h>
25 #include <linux/dma-mapping.h>
40 #include <linux/firmware/xlnx-zynqmp.h>
58 * (bp)->rx_ring_size)
64 * (bp)->tx_ring_size)
67 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
78 …MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN -…
80 * false amba_error in TX path from the DMA assuming there is not enough
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Dmacb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Atmel Corporation
114 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
115 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
116 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
117 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
118 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
135 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
136 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
137 #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
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