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Searched +full:rk3036 +full:- +full:power (Results 1 – 21 of 21) sorted by relevance

/linux-6.14.4/arch/arm/boot/dts/rockchip/
Drk3036.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
9 #include <dt-bindings/power/rk3036-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
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Drk3036-kylin.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include "rk3036.dtsi"
8 model = "Rockchip RK3036 KylinBoard";
9 compatible = "rockchip,rk3036-kylin", "rockchip,rk3036";
12 stdout-path = "serial2:115200n8";
20 hdmi_con: hdmi-con {
21 compatible = "hdmi-connector";
26 remote-endpoint = <&hdmi_out_con>;
31 leds: gpio-leds {
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Drk3128.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3128-power.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
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/linux-6.14.4/Documentation/devicetree/bindings/display/rockchip/
Drockchip,inno-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,inno-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <[email protected]>
16 - rockchip,rk3036-inno-hdmi
17 - rockchip,rk3128-inno-hdmi
28 - description: The HDMI controller main clock
29 - description: The HDMI PHY reference clock
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Drockchip-vop.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <[email protected]>
21 - rockchip,px30-vop-big
22 - rockchip,px30-vop-lit
23 - rockchip,rk3036-vop
24 - rockchip,rk3066-vop
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/linux-6.14.4/Documentation/devicetree/bindings/mtd/
Drockchip,nand-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/rockchip,nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: nand-controller.yaml#
13 - Heiko Stuebner <[email protected]>
18 - const: rockchip,px30-nfc
19 - const: rockchip,rk2928-nfc
20 - const: rockchip,rv1108-nfc
21 - items:
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/linux-6.14.4/Documentation/devicetree/bindings/power/
Drockchip,power-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip Power Domains
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <[email protected]>
14 Rockchip processors include support for multiple power domains
16 application scenarios to save power.
18 Power domains contained within power-controller node are
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/linux-6.14.4/Documentation/devicetree/bindings/gpu/
Darm,mali-utgard.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <[email protected]>
11 - Maxime Ripard <[email protected]>
12 - Heiko Stuebner <[email protected]>
16 pattern: '^gpu@[a-f0-9]+$'
19 - items:
20 - const: allwinner,sun8i-a23-mali
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/linux-6.14.4/Documentation/devicetree/bindings/soc/rockchip/
Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <[email protected]>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
19 - rockchip,rk3568-pcie3-phy-grf
20 - rockchip,rk3568-pipe-grf
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/linux-6.14.4/Documentation/devicetree/bindings/media/
Drockchip-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/rockchip-vpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ezequiel Garcia <[email protected]>
18 - enum:
19 - rockchip,rk3036-vpu
20 - rockchip,rk3066-vpu
21 - rockchip,rk3288-vpu
22 - rockchip,rk3328-vpu
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/linux-6.14.4/Documentation/devicetree/bindings/spi/
Dspi-rockchip.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-rockchip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - $ref: spi-controller.yaml#
17 - Heiko Stuebner <[email protected]>
23 - const: rockchip,rk3036-spi
24 - const: rockchip,rk3066-spi
25 - const: rockchip,rk3228-spi
26 - const: rockchip,rv1108-spi
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/linux-6.14.4/Documentation/devicetree/bindings/sound/
Drockchip-i2s.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The I2S bus (Inter-IC sound bus) is a serial link for digital
14 - Heiko Stuebner <[email protected]>
17 - $ref: dai-common.yaml#
22 - const: rockchip,rk3066-i2s
23 - items:
24 - enum:
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/linux-6.14.4/Documentation/devicetree/bindings/mmc/
Drockchip-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 controller that are not already included in the synopsys-dw-mshc-common.yaml
17 - $ref: synopsys-dw-mshc-common.yaml#
20 - Heiko Stuebner <[email protected]>
27 - const: rockchip,rk2928-dw-mshc
29 - const: rockchip,rk3288-dw-mshc
30 - items:
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/linux-6.14.4/sound/soc/codecs/
Dinno_rk3036.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Driver of Inno Codec for rk3036 by Rockchip Inc.
5 * Author: Zheng ShunQian<zhengsq@rock-chips.com>
29 #define INNO_R00_PRB_DISABLE (0x0 << 6) /*power reset bypass*/
90 /* Gain of output, 1.5db step: -39db(0x0) ~ 0db(0x1a) ~ 6db(0x1f) */
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
5 # setting - SPI can't be modular so that case doesn't need to be covered.
489 tristate "Analog Devices AU1761 CODEC - I2C"
495 tristate "Analog Devices AU1761 CODEC - SPI"
532 tristate "Analog Devices ADAU7002 Stereo PDM-to-I2S/TDM Converter"
538 tristate "Analog Devices ADAU7118 8 Channel PDM-to-I2S/TDM Converter - HW Mode"
541 Enable support for the Analog Devices ADAU7118 8 Channel PDM-to-I2S/TDM
547 will be called snd-soc-adau7118-hw.
550 tristate "Analog Devices ADAU7118 8 Channel PDM-to-I2S/TDM Converter - I2C"
555 Enable support for the Analog Devices ADAU7118 8 Channel PDM-to-I2S/TDM
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/linux-6.14.4/Documentation/devicetree/bindings/usb/
Ddwc2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <[email protected]>
13 - $ref: usb-drd.yaml#
14 - $ref: usb-hcd.yaml#
19 - const: brcm,bcm2835-usb
20 - const: hisilicon,hi6220-usb
21 - const: ingenic,jz4775-otg
22 - const: ingenic,jz4780-otg
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/linux-6.14.4/arch/arm/mach-rockchip/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
57 np = dev->of_node; in rockchip_get_core_reset()
77 * We need to soft reset the cpu when we turn off the cpu power domain, in pmu_set_power_domain()
87 pr_err("%s: could not update power domain\n", in pmu_set_power_domain()
92 ret = -1; in pmu_set_power_domain()
96 pr_err("%s: could not read power domain state\n", in pmu_set_power_domain()
122 return -ENXIO; in rockchip_boot_secondary()
128 return -ENXIO; in rockchip_boot_secondary()
159 * rockchip_smp_prepare_sram - populate necessary sram block
160 * Starting cores execute the code residing at the start of the on-chip sram
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/linux-6.14.4/Documentation/devicetree/bindings/arm/
Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <[email protected]>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
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/linux-6.14.4/drivers/mtd/nand/raw/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 <http://www.linux-mtd.infradead.org/doc/nand.html>.
102 selected to save power. This will mean there is a small delay
104 approximately 5mA of power when there is nothing happening.
126 include NAND flash controllers with built-in hardware ECC
161 - PXA3xx processors (NFCv1)
162 - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2)
163 - 64-bit Aramda platforms (7k, 8k, ac5) (NFCv2)
229 Controller Module with built-in hardware ECC capabilities.
240 with built-in hardware ECC capabilities.
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/linux-6.14.4/drivers/pmdomain/rockchip/
Dpm-domains.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip Generic power domain support.
23 #include <dt-bindings/power/px30-power.h>
24 #include <dt-bindings/power/rockchip,rv1126-power.h>
25 #include <dt-bindings/power/rk3036-power.h>
26 #include <dt-bindings/power/rk3066-power.h>
27 #include <dt-bindings/power/rk3128-power.h>
28 #include <dt-bindings/power/rk3188-power.h>
29 #include <dt-bindings/power/rk3228-power.h>
30 #include <dt-bindings/power/rk3288-power.h>
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/linux-6.14.4/drivers/clk/rockchip/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
56 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
68 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_pll_round_rate()
72 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_round_rate()
78 return rate_table[i - 1].rate; in rockchip_pll_round_rate()
88 struct regmap *grf = pll->ctx->grf; in rockchip_pll_wait_lock()
92 ret = regmap_read_poll_timeout(grf, pll->lock_offset, val, in rockchip_pll_wait_lock()
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