1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM Mali Utgard GPU 8 9maintainers: 10 - Rob Herring <[email protected]> 11 - Maxime Ripard <[email protected]> 12 - Heiko Stuebner <[email protected]> 13 14properties: 15 $nodename: 16 pattern: '^gpu@[a-f0-9]+$' 17 compatible: 18 oneOf: 19 - items: 20 - const: allwinner,sun8i-a23-mali 21 - const: allwinner,sun7i-a20-mali 22 - const: arm,mali-400 23 - items: 24 - enum: 25 - allwinner,sun4i-a10-mali 26 - allwinner,sun7i-a20-mali 27 - allwinner,sun8i-h3-mali 28 - allwinner,sun8i-r40-mali 29 - allwinner,sun50i-a64-mali 30 - rockchip,rk3036-mali 31 - rockchip,rk3066-mali 32 - rockchip,rk3128-mali 33 - rockchip,rk3188-mali 34 - rockchip,rk3228-mali 35 - samsung,exynos4210-mali 36 - st,stih410-mali 37 - stericsson,db8500-mali 38 - xlnx,zynqmp-mali 39 - const: arm,mali-400 40 - items: 41 - enum: 42 - allwinner,sun50i-h5-mali 43 - amlogic,meson8-mali 44 - amlogic,meson8b-mali 45 - amlogic,meson-gxbb-mali 46 - amlogic,meson-gxl-mali 47 - hisilicon,hi6220-mali 48 - mediatek,mt7623-mali 49 - rockchip,rk3328-mali 50 - const: arm,mali-450 51 52 # "arm,mali-300" 53 54 reg: 55 maxItems: 1 56 57 interrupts: 58 minItems: 4 59 maxItems: 20 60 61 interrupt-names: 62 allOf: 63 - additionalItems: true 64 minItems: 4 65 maxItems: 20 66 items: 67 # At least enforce the first 2 interrupts 68 - const: gp 69 - const: gpmmu 70 - items: 71 # Not ideal as any order and combination are allowed 72 enum: 73 - gp # Geometry Processor interrupt 74 - gpmmu # Geometry Processor MMU interrupt 75 - pp # Pixel Processor broadcast interrupt (mali-450 only) 76 - pp0 # Pixel Processor X interrupt (X from 0 to 7) 77 - ppmmu0 # Pixel Processor X MMU interrupt (X from 0 to 7) 78 - pp1 79 - ppmmu1 80 - pp2 81 - ppmmu2 82 - pp3 83 - ppmmu3 84 - pp4 85 - ppmmu4 86 - pp5 87 - ppmmu5 88 - pp6 89 - ppmmu6 90 - pp7 91 - ppmmu7 92 - pmu # Power Management Unit interrupt (optional) 93 - combined # stericsson,db8500-mali only 94 95 clocks: 96 maxItems: 2 97 98 clock-names: 99 items: 100 - const: bus 101 - const: core 102 103 memory-region: true 104 105 mali-supply: true 106 107 opp-table: 108 type: object 109 110 power-domains: 111 maxItems: 1 112 113 resets: 114 maxItems: 1 115 116 operating-points-v2: true 117 118 "#cooling-cells": 119 const: 2 120 121required: 122 - compatible 123 - reg 124 - interrupts 125 - interrupt-names 126 - clocks 127 - clock-names 128 129additionalProperties: false 130 131allOf: 132 - if: 133 properties: 134 compatible: 135 contains: 136 enum: 137 - allwinner,sun4i-a10-mali 138 - allwinner,sun7i-a20-mali 139 - allwinner,sun8i-r40-mali 140 - allwinner,sun50i-a64-mali 141 - allwinner,sun50i-h5-mali 142 - amlogic,meson8-mali 143 - amlogic,meson8b-mali 144 - hisilicon,hi6220-mali 145 - mediatek,mt7623-mali 146 - rockchip,rk3036-mali 147 - rockchip,rk3066-mali 148 - rockchip,rk3188-mali 149 - rockchip,rk3228-mali 150 - rockchip,rk3328-mali 151 then: 152 required: 153 - resets 154 155examples: 156 - | 157 #include <dt-bindings/interrupt-controller/irq.h> 158 #include <dt-bindings/interrupt-controller/arm-gic.h> 159 160 mali: gpu@1c40000 { 161 compatible = "allwinner,sun7i-a20-mali", "arm,mali-400"; 162 reg = <0x01c40000 0x10000>; 163 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 170 interrupt-names = "gp", 171 "gpmmu", 172 "pp0", 173 "ppmmu0", 174 "pp1", 175 "ppmmu1", 176 "pmu"; 177 clocks = <&ccu 1>, <&ccu 2>; 178 clock-names = "bus", "core"; 179 resets = <&ccu 1>; 180 #cooling-cells = <2>; 181 }; 182 183... 184