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/linux-6.14.4/Documentation/devicetree/bindings/w1/
Dw1-uart.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/w1/w1-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART 1-Wire Bus
10 - Christoph Winklhofer <[email protected]>
13 UART 1-wire bus. Utilizes the UART interface via the Serial Device Bus
14 to create the 1-Wire timing patterns.
16 The UART peripheral must support full-duplex and operate in open-drain
18 baud-rate and transmitted byte, which corresponds to a 1-Wire read bit,
[all …]
/linux-6.14.4/arch/m68k/atari/
Ddebug.c6 * Assembled of parts of former atari/config.c 97-12-18 by Roman Hodek
23 /* Can be set somewhere, if a SCC master reset has already be done and should
31 .index = -1,
45 while (count--) { in atari_mfp_console_write()
64 while (count--) { in atari_scc_console_write()
81 while (count--) { in atari_midi_console_write()
91 /* This a some-seconds timeout in case no printer is connected */ in ata_par_out()
94 while ((st_mfp.par_dt_reg & 1) && --i) /* wait for BUSY == L */ in ata_par_out()
117 while (count--) { in atari_par_console_write()
164 * timer values for 1200...115200 bps; > 38400 select 110, 134, or 150 in atari_init_mfp_port()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dlantiq,pef2256.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <[email protected]>
20 - const: lantiq,pef2256
27 - description: Master Clock
28 - description: System Clock Receive
29 - description: System Clock Transmit
31 clock-names:
33 - const: mclk
[all …]
/linux-6.14.4/drivers/soundwire/
Dgeneric_bandwidth_allocation.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 // Copyright(c) 2015-2020 Intel Corporation.
40 unsigned int rate, bps, ch = 0; in sdw_compute_slave_ports() local
42 struct sdw_bus_params *b_params = &m_rt->bus->params; in sdw_compute_slave_ports()
44 port_bo = t_data->block_offset; in sdw_compute_slave_ports()
46 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in sdw_compute_slave_ports()
47 rate = m_rt->stream->params.rate; in sdw_compute_slave_ports()
48 bps = m_rt->stream->params.bps; in sdw_compute_slave_ports()
49 sample_int = (m_rt->bus->params.curr_dr_freq / rate); in sdw_compute_slave_ports()
52 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { in sdw_compute_slave_ports()
[all …]
Dstream.c1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2 // Copyright(c) 2015-18 Intel Corporation.
5 * stream.c - SoundWire Bus stream operations.
71 if (bus->params.next_bank) { in _sdw_program_slave_port_params()
72 addr1 = SDW_DPN_OFFSETCTRL2_B1(t_params->port_num); in _sdw_program_slave_port_params()
73 addr2 = SDW_DPN_BLOCKCTRL3_B1(t_params->port_num); in _sdw_program_slave_port_params()
74 addr3 = SDW_DPN_SAMPLECTRL2_B1(t_params->port_num); in _sdw_program_slave_port_params()
75 addr4 = SDW_DPN_HCTRL_B1(t_params->port_num); in _sdw_program_slave_port_params()
77 addr1 = SDW_DPN_OFFSETCTRL2_B0(t_params->port_num); in _sdw_program_slave_port_params()
78 addr2 = SDW_DPN_BLOCKCTRL3_B0(t_params->port_num); in _sdw_program_slave_port_params()
[all …]
Damd_manager.c1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
5 * Copyright 2023-24 Advanced Micro Devices, Inc.
35 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN); in amd_init_sdw_manager()
36 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US, in amd_init_sdw_manager()
41 /* SoundWire manager bus reset */ in amd_init_sdw_manager()
42 writel(AMD_SDW_BUS_RESET_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL); in amd_init_sdw_manager()
43 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, in amd_init_sdw_manager()
48 writel(AMD_SDW_BUS_RESET_CLEAR_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL); in amd_init_sdw_manager()
49 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, !val, in amd_init_sdw_manager()
52 dev_err(amd_manager->dev, "Failed to reset SoundWire manager instance%d\n", in amd_init_sdw_manager()
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/amdgpu/
Damdgpu_ras.c101 if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT || in get_ras_block_str()
102 ras_block->block >= ARRAY_SIZE(ras_block_string)) in get_ras_block_str()
105 if (ras_block->block == AMDGPU_RAS_BLOCK__MCA) in get_ras_block_str()
106 return ras_mca_block_string[ras_block->sub_block_index]; in get_ras_block_str()
108 return ras_block_string[ras_block->block]; in get_ras_block_str()
154 amdgpu_ras_get_context(adev)->error_query_ready = ready; in amdgpu_ras_set_error_query_ready()
160 return amdgpu_ras_get_context(adev)->error_query_ready; in amdgpu_ras_get_error_query_ready()
171 if ((address >= adev->gmc.mc_vram_size) || in amdgpu_reserve_page_direct()
173 dev_warn(adev->dev, in amdgpu_reserve_page_direct()
176 return -EINVAL; in amdgpu_reserve_page_direct()
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Damdgpu_virt.c43 vf2pf_info->ucode_info[ucode].id = ucode; \
44 vf2pf_info->ucode_info[ucode].version = ver; \
60 if (adev->asic_type != CHIP_ALDEBARAN && in amdgpu_virt_init_setting()
61 adev->asic_type != CHIP_ARCTURUS && in amdgpu_virt_init_setting()
62 ((adev->pdev->class >> 8) != PCI_CLASS_ACCELERATOR_PROCESSING)) { in amdgpu_virt_init_setting()
63 if (adev->mode_info.num_crtc == 0) in amdgpu_virt_init_setting()
64 adev->mode_info.num_crtc = 1; in amdgpu_virt_init_setting()
65 adev->enable_virtual_display = true; in amdgpu_virt_init_setting()
67 ddev->driver_features &= ~DRIVER_ATOMIC; in amdgpu_virt_init_setting()
68 adev->cg_flags = 0; in amdgpu_virt_init_setting()
[all …]
/linux-6.14.4/include/media/i2c/
Dtc358743.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * tc358743 - Toshiba HDMI to CSI-2 bridge
10 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
11 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
51 /* Bps pr lane is (refclk_hz / pll_prd) * pll_fbd */
61 * bps pr lane is 823.5 MHz, and can serve as a starting point.
73 /* DVI->HDMI detection delay to avoid unnecessary switching between DVI
80 /* Reset PHY automatically when TMDS clock goes from DC to AC.
86 /* Reset PHY automatically when TMDS clock passes 21 MHz.
92 /* Reset PHY automatically when TMDS clock is detected.
[all …]
/linux-6.14.4/drivers/tty/serial/
Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) argument
58 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
60 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
61 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
62 #define ERR_RES 0x30 /* Error Reset */
63 #define RES_H_IUS 0x38 /* Reset highest IUS */
65 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
66 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
67 #define RES_EOM_L 0xC0 /* Reset EOM latch */
[all …]
Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) argument
50 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
52 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
53 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
54 #define ERR_RES 0x30 /* Error Reset */
55 #define RES_H_IUS 0x38 /* Reset highest IUS */
57 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
58 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
59 #define RES_EOM_L 0xC0 /* Reset EOM latch */
[all …]
Dzs.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) argument
79 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
81 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
82 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
83 #define ERR_RES 0x30 /* Error Reset */
84 #define RES_H_IUS 0x38 /* Reset highest IUS */
86 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
87 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
[all …]
Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
[all …]
Dsh-sci.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 * Copyright (C) 2002 - 2011 Paul Mundt
9 * based off of the old drivers/char/sh-sci.c by:
26 #include <linux/dma-mapping.h>
40 #include <linux/reset.h>
58 #include "sh-sci.h"
60 /* Offsets into the sci_port->irqs array */
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
[all …]
/linux-6.14.4/drivers/w1/masters/
Dw1-uart.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * w1-uart - UART 1-Wire bus driver
5 * Uses the UART interface (via Serial Device Bus) to create the 1-Wire
6 * timing patterns. Implements the following 1-Wire master interface:
8 * - reset_bus: requests baud-rate 9600
10 * - touch_bit: requests baud-rate 115200
27 /* Timeout to wait for completion of serdev-receive */
31 * struct w1_uart_config - configuration for 1-Wire operation
32 * @baudrate: baud-rate returned from serdev
33 * @delay_us: delay to complete a 1-Wire cycle (in us)
[all …]
/linux-6.14.4/Documentation/netlink/specs/
Dnet_shaper.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
2 name: net-shaper
25 Existing shapers can be deleted/reset via the @delete operation.
32 @cap-get operation.
35 -
39 render-max: true
41 - name: unspec
43 -
46 -
51 -
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/media/i2c/
Dtc358743.txt1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
18 - clock-lanes: should be <0>
[all …]
/linux-6.14.4/drivers/net/hamradio/
Dbaycom_epp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * baycom_epp.c -- baycom epp radio modem driver.
7 * Copyright (C) 1998-2000
21 * removed some pre-2.2 kernel compatibility cruft
28 #include <linux/crc-ccitt.h>
45 /* --------------------------------------------------------------------- */
50 /* --------------------------------------------------------------------- */
56 static const char bc_drvinfo[] = KERN_INFO "baycom_epp: (C) 1998-2000 Thomas Sailer, HB9JNX/AE4WA\n"
59 /* --------------------------------------------------------------------- */
65 /* --------------------------------------------------------------------- */
[all …]
/linux-6.14.4/drivers/net/can/dev/
Dcalc_bittiming.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2005 Marc Kleine-Budde, Pengutronix
4 * Copyright (C) 2008-2009 Wolfgang Grandegger <[email protected]>
10 #define CAN_CALC_MAX_ERROR 50 /* in one-tenth of a percent */
12 /* Bit-timing calculation derived from:
15 * Copyright 2004-2006 Pavel Pisa - DCE FELK CVUT cz
19 * Calculates proper bit-timing parameters for a specified bit-rate
20 * and sample-point, which can then be used to set the bit-timing
36 tseg2 = tseg + CAN_SYNC_SEG - in can_update_sample_point()
38 1000 - i; in can_update_sample_point()
[all …]
/linux-6.14.4/sound/hda/
Dhdac_device.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * HD-audio codec core device
28 * snd_hdac_device_init - initialize the HD-audio codec base device
48 dev = &codec->dev; in snd_hdac_device_init()
50 dev->parent = bus->dev; in snd_hdac_device_init()
51 dev->bus = &snd_hda_bus_type; in snd_hdac_device_init()
52 dev->release = default_release; in snd_hdac_device_init()
53 dev->groups = hdac_dev_attr_groups; in snd_hdac_device_init()
57 codec->bus = bus; in snd_hdac_device_init()
58 codec->addr = addr; in snd_hdac_device_init()
[all …]
/linux-6.14.4/include/linux/soundwire/
Dsdw.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
85 * enum sdw_slave_status - Slave status
103 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
104 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
114 * enum sdw_command_response - Command response as defined by SDW spec
200 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
211 * enum sdw_dpn_type - Data port types
226 * enum sdw_clk_stop_mode - Clock Stop modes
229 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode,
[all …]
/linux-6.14.4/include/uapi/linux/
Datmdev.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* atmdev.h - ATM device driver declarations and various related items */
4 /* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */
19 /* OC3 link rate: 155520000 bps
23 #define ATM_25_PCR ((25600000/8-8000)/54)
26 /* OC12 link rate: 622080000 bps
66 /* reset itf's ATM address list */
97 /* enable or disable single-copy */
109 * above. In the future we may support dynamic loading of these - for now,
113 #define ATM_BACKEND_PPP 1 /* PPPoATM - RFC2364 */
[all …]
Dscc.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
14 #define PRIMUS 0x04 /* hardware type for PRIMUS-PC (DG9BL) card */
55 PARAM_RETURN = 255 /* reset kiss mode */
102 TXS_NEWFRAME, /* reset CRC and send (next) frame */
135 long speed; /* Line speed, bps */
141 int command; /* one of the KISS-Commands defined above */
142 unsigned param; /* KISS-Param */
150 io_port vector_latch; /* INTACK-Latch (#) */
/linux-6.14.4/drivers/usb/serial/
Dcypress_m8.c1 // SPDX-License-Identifier: GPL-2.0+
10 * See Documentation/usb/usb-serial.rst for more information on using this
104 __u8 current_status; /* received from last read - info on dsr,cts,cd,ri,etc */
106 __u8 rx_flags; /* throttling - used from whiteheat/ftdi_sio */
170 .description = "HID->COM RS232 Adapter",
195 .description = "Nokia CA-42 V2 Adapter",
225 /* FRWD Dongle hidcom needs to skip reset and speed checks */
228 return ((le16_to_cpu(dev->descriptor.idVendor) == VENDOR_ID_FRWD) && in is_frwd()
229 (le16_to_cpu(dev->descriptor.idProduct) == PRODUCT_ID_CYPHIDCOM_FRWD)); in is_frwd()
240 /* FRWD Dongle uses 115200 bps */ in analyze_baud_rate()
[all …]
/linux-6.14.4/drivers/net/ethernet/marvell/
Dmvneta_bm.c32 writel(data, priv->reg_base + offset); in mvneta_bm_write()
37 return readl(priv->reg_base + offset); in mvneta_bm_read()
96 (struct mvneta_bm_pool *)hwbm_pool->priv; in mvneta_bm_construct()
97 struct mvneta_bm *priv = bm_pool->priv; in mvneta_bm_construct()
105 phys_addr = dma_map_single(&priv->pdev->dev, buf, bm_pool->buf_size, in mvneta_bm_construct()
107 if (unlikely(dma_mapping_error(&priv->pdev->dev, phys_addr))) in mvneta_bm_construct()
108 return -ENOMEM; in mvneta_bm_construct()
119 struct platform_device *pdev = priv->pdev; in mvneta_bm_pool_create()
122 size_bytes = sizeof(u32) * bm_pool->hwbm_pool.size; in mvneta_bm_pool_create()
123 bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, size_bytes, in mvneta_bm_pool_create()
[all …]

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