Lines Matching +full:reset +full:- +full:bps

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * tc358743 - Toshiba HDMI to CSI-2 bridge
10  * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
11  * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
51 	/* Bps pr lane is (refclk_hz / pll_prd) * pll_fbd */
61 	 * bps pr lane is 823.5 MHz, and can serve as a starting point.
73 	/* DVI->HDMI detection delay to avoid unnecessary switching between DVI
80 	/* Reset PHY automatically when TMDS clock goes from DC to AC.
86 	/* Reset PHY automatically when TMDS clock passes 21 MHz.
92 	/* Reset PHY automatically when TMDS clock is detected.
98 	/* Reset HDMI PHY automatically when hsync period is out of range.
104 	/* Reset HDMI PHY automatically when vsync period is out of range.