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/linux-6.14.4/arch/loongarch/boot/dts/
Dloongson-2k1000-ref.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include "loongson-2k1000.dtsi"
11 compatible = "loongson,ls2k1000-ref", "loongson,ls2k1000";
12 model = "Loongson-2K1000 Reference Board";
19 stdout-path = "serial0:115200n8";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
35 compatible = "shared-dma-pool";
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/pinctrl/
Dloongson,ls2k-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/loongson,ls2k-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-2 SoC Pinctrl Controller
10 - zhanghongchen <[email protected]>
11 - Yinbo Zhu <[email protected]>
14 - $ref: pinctrl.yaml#
18 const: loongson,ls2k-pinctrl
24 '-pins$':
[all …]
Dnvidia,tegra234-pinmux-aon.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-aon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra234 AON Pinmux Controller
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
15 const: nvidia,tegra234-pinmux-aon
21 "^pinmux(-[a-z0-9-]+)?$":
26 $ref: nvidia,tegra234-pinmux-common.yaml
[all …]
Dbrcm,ns-pinmux.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/brcm,ns-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafał Miłecki <[email protected]>
23 - brcm,bcm4708-pinmux
24 - brcm,bcm4709-pinmux
25 - brcm,bcm53012-pinmux
30 reg-names:
34 '-pins$':
[all …]
Dintel,lgm-io.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Lightning Mountain SoC pinmux & GPIO controller
10 - Rahul Tanwar <[email protected]>
13 Pinmux & GPIO controller controls pin multiplexing & configuration including
18 const: intel,lgm-io
25 '-pins$':
30 $ref: pinmux-node.yaml#
[all …]
Dsophgo,cv1800-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/sophgo,cv1800-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inochi Amaoto <[email protected]>
15 - sophgo,cv1800b-pinctrl
16 - sophgo,cv1812h-pinctrl
17 - sophgo,sg2000-pinctrl
18 - sophgo,sg2002-pinctrl
22 - description: pinctrl for system domain
[all …]
Dnxp,s32g2-siul2-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/nxp,s32g2-siul2-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ghennadi Procopciuc <[email protected]>
12 - Chester Lin <[email protected]>
15 S32G2 pinmux is implemented in SIUL2 (System Integration Unit Lite2),
21 IMCR registers need to be revealed for kernel to configure pinmux.
24 MSCR102-MSCR111, MSCR123-MSCR143, IMCR84-IMCR118 and IMCR398-IMCR429.
29 - nxp,s32g2-siul2-pinctrl
[all …]
Drenesas,rzn1-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrizio Castro <[email protected]>
11 - Geert Uytterhoeven <[email protected]>
16 - enum:
17 - renesas,r9a06g032-pinctrl # RZ/N1D
18 - renesas,r9a06g033-pinctrl # RZ/N1S
19 - const: renesas,rzn1-pinctrl # Generic RZ/N1
[all …]
Dnvidia,tegra234-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra234 Pinmux Controller
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
15 const: nvidia,tegra234-pinmux
21 "^pinmux(-[a-z0-9-]+)?$":
26 $ref: nvidia,tegra234-pinmux-common.yaml
[all …]
Dnvidia,tegra210-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra210-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 Pinmux Controller
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
15 const: nvidia,tegra210-pinmux
19 - description: APB_MISC_GP_*_PADCTRL register (pad control)
20 - description: PINMUX_AUX_* registers (pinmux)
[all …]
Dpinmux-node.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <[email protected]>
50 For cases like this, the pin controller driver may use pinctrl-pin-array helper
55 #pinctrl-cells = <2>;
58 pinctrl-pin-array = <
67 Above #pinctrl-cells specifies the number of value cells in addition to the
68 index of the registers. This is similar to the interrupts-extended binding with
[all …]
Dnvidia,tegra124-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra124-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra124 Pinmux Controller
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
14 Tegra30 pinctrl binding, as described in nvidia,tegra20-pinmux.yaml and
15 nvidia,tegra30-pinmux.yaml. In fact, this document assumes that binding as a
21 - const: nvidia,tegra124-pinmux
[all …]
Dmediatek,mt65xx-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <[email protected]>
18 - mediatek,mt2701-pinctrl
19 - mediatek,mt2712-pinctrl
20 - mediatek,mt6397-pinctrl
21 - mediatek,mt7623-pinctrl
22 - mediatek,mt8127-pinctrl
[all …]
Dnvidia,tegra114-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra114-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra114 pinmux Controller
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
15 const: nvidia,tegra114-pinmux
19 - description: pad control registers
20 - description: mux registers
[all …]
Dnvidia,tegra194-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra194-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 Pinmux Controller
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
16 - nvidia,tegra194-pinmux
17 - nvidia,tegra194-pinmux-aon
21 - description: pinmux registers
[all …]
Drenesas,rza2-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Brandt <[email protected]>
11 - Geert Uytterhoeven <[email protected]>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
23 const: renesas,r7s9210-pinctrl # RZ/A2M
28 gpio-controller: true
30 '#gpio-cells':
[all …]
Dmediatek,mt8195-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <[email protected]>
17 const: mediatek,mt8195-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
32 gpio-line-names: true
[all …]
Dnvidia,tegra20-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra20-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 Pinmux Controller
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
15 const: nvidia,tegra20-pinmux
19 - description: tri-state registers
20 - description: mux register
[all …]
/linux-6.14.4/arch/arm64/boot/dts/mediatek/
Dmt6797.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/clock/mt6797-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
14 interrupt-parent = <&sysirq>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <1>;
[all …]
Dmt8365-evk.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021-2022 BayLibre, SAS.
10 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/pinctrl/mt8365-pinfunc.h>
20 compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
28 stdout-path = "serial0:921600n8";
33 compatible = "linaro,optee-tz";
38 gpio-keys {
[all …]
Dmt2712-evb.dts5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
14 chassis-type = "embedded";
15 compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
27 stdout-path = "serial0:921600n8";
30 cpus_fixed_vproc0: regulator-vproc-buck0 {
31 compatible = "regulator-fixed";
32 regulator-name = "vproc_buck0";
33 regulator-min-microvolt = <1000000>;
[all …]
/linux-6.14.4/arch/arm/boot/dts/microchip/
Dat91-kizbox3-hs.dts1 // SPDX-License-Identifier: GPL-2.0
3 * at91-kizbox3-hs.dts - Device Tree file for Overkiz KIZBOX3-HS board
11 /dts-v1/;
12 #include "at91-kizbox3_common.dtsi"
15 model = "Overkiz KIZBOX3-HS";
16 compatible = "overkiz,kizbox3-hs", "atmel,sama5d2", "atmel,sama5";
18 led-controller-1 {
21 led-1 {
25 led-2 {
29 led-3 {
[all …]
/linux-6.14.4/drivers/pinctrl/
Dpinctrl-equilibrium.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pinctrl/pinconf-generic.h>
12 #include <linux/pinctrl/pinmux.h>
18 #include "pinmux.h"
19 #include "pinctrl-equilibrium.h"
21 #define PIN_NAME_FMT "io-%d"
32 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
33 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); in eqbr_gpio_disable_irq()
34 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
45 gc->direction_input(gc, offset); in eqbr_gpio_enable_irq()
[all …]
/linux-6.14.4/arch/arm64/boot/dts/freescale/
Ds32g2.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 * Copyright 2017-2021, 2024 NXP
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
23 compatible = "arm,scmi-shmem";
[all …]
/linux-6.14.4/arch/arm/boot/dts/mediatek/
Dmt2701-evb.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
14 compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
22 compatible = "mediatek,mt2701-cs42448-machine";
25 audio-routing =
42 mediatek,audio-codec = <&cs42448>;
43 mediatek,audio-codec-bt-mrg = <&bt_sco_codec>;
44 pinctrl-names = "default";
45 pinctrl-0 = <&aud_pins_default>;
[all …]

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