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/linux-6.14.4/sound/pci/ca0106/
Dca0106.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2004 James Courtier-Dutton <[email protected]>
11 * Support interrupts per period.
12 * Removed noise from Center/LFE channel when in Analog mode.
50 * Implement support for Line-in capture on SB Live 24bit.
73 #define IPR_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
74 #define IPR_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */
87 #define IPR_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */
88 #define IPR_MIDI_TX_A 0x00000002 /* MIDI UART-A Transmit buffer empty */
93 #define INTE_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
[all …]
/linux-6.14.4/include/linux/
Drelay.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2002, 2003 - Tom Zanussi ([email protected]), IBM Corp
6 * Copyright (C) 1999, 2000, 2001, 2002 - Karim Yaghmour ([email protected])
32 * Per-cpu relay channel buffer
36 void *start; /* start of channel buffer */
37 void *data; /* start of current sub-buffer */
38 size_t offset; /* current offset into sub-buffer */
39 size_t subbufs_produced; /* count of sub-buffers produced */
40 size_t subbufs_consumed; /* count of sub-buffers consumed */
41 struct rchan *chan; /* associated channel */
[all …]
/linux-6.14.4/drivers/edac/
Dskx_common.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define SKX_NUM_IMC 2 /* Memory controllers per socket */
33 #define SKX_NUM_CHANNELS 3 /* Channels per memory controller */
34 #define SKX_NUM_DIMMS 2 /* Max DIMMS per channel */
60 * Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding"
68 * cccc = channel
72 * Errors from either the memory of the 1-level memory system or the
73 * 2nd level memory (the slow "far" memory) of the 2-level memory system.
78 * of the 2-level memory system.
111 int num_channels; /* channels per memory controller */
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/iio/afe/
Dtemperature-transducer.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/afe/temperature-transducer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Beguin <[email protected]>
19 When an io-channel measures the output voltage of a temperature analog front
35 -----
37 +---+---+
39 +---+---+ -----
41 V proportional to T +----+----+
[all …]
Dtemperature-sense-rtd.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/afe/temperature-sense-rtd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Beguin <[email protected]>
17 When an io-channel measures the output voltage across an RTD such as a
25 T = 1 / (alpha * r0 * iexc) * (V - r0 * iexc)
30 -----
32 +---+----+
34 +---+----+
[all …]
/linux-6.14.4/drivers/hwmon/
Dnct7904.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * nct7904.c - driver for Nuvoton NCT7904D.
59 #define VSEN1_HV_LL_REG 0x02 /* Bank 1; 2 regs (HV/LV) per sensor */
60 #define VSEN1_LV_LL_REG 0x03 /* Bank 1; 2 regs (HV/LV) per sensor */
61 #define VSEN1_HV_HL_REG 0x00 /* Bank 1; 2 regs (HV/LV) per sensor */
62 #define VSEN1_LV_HL_REG 0x01 /* Bank 1; 2 regs (HV/LV) per sensor */
69 #define VSEN1_HV_REG 0x40 /* Bank 0; 2 regs (HV/LV) per sensor */
79 #define TEMP_CH1_C_REG 0x04 /* Bank 1; 1 reg per sensor */
80 #define DTS_T_CPU1_C_REG 0x90 /* Bank 1; 1 reg per sensor */
81 #define DTS_T_CPU1_CH_REG 0x91 /* Bank 1; 1 reg per sensor */
[all …]
Dmax6639.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * max6639.c - Support for Maxim MAX6639
5 * 2-Channel Temperature Monitor with Dual PWM Fan-Speed Controller
19 #include <linux/hwmon-sysfs.h>
28 /* The MAX6639 registers, valid channel numbers: 0, 1 */
81 u8 ppr[MAX6639_NUM_CHANNELS]; /* Pulses per rotation 0..3 for 1..4 ppr */
88 static int max6639_temp_read_input(struct device *dev, int channel, long *temp) in max6639_temp_read_input() argument
90 u32 regs[2] = { MAX6639_REG_TEMP_EXT(channel), MAX6639_REG_TEMP(channel) }; in max6639_temp_read_input()
95 res = regmap_multi_reg_read(data->regmap, regs, regvals, 2); in max6639_temp_read_input()
104 static int max6639_temp_read_fault(struct device *dev, int channel, long *fault) in max6639_temp_read_fault() argument
[all …]
/linux-6.14.4/Documentation/scsi/
Dadvansys.rst1 .. SPDX-License-Identifier: GPL-2.0
8 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
9 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
10 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
21 - ABP-480 - Bus-Master CardBus (16 CDB)
24 - ABP510/5150 - Bus-Master ISA (240 CDB)
25 - ABP5140 - Bus-Master ISA PnP (16 CDB)
26 - ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
27 - ABP902/3902 - Bus-Master PCI (16 CDB)
28 - ABP3905 - Bus-Master PCI (16 CDB)
[all …]
/linux-6.14.4/Documentation/filesystems/
Drelay.rst1 .. SPDX-License-Identifier: GPL-2.0
9 to userspace via user-defined 'relay channels'.
11 A 'relay channel' is a kernel->user data relay mechanism implemented
12 as a set of per-cpu kernel buffers ('channel buffers'), each
14 clients write into the channel buffers using efficient write
15 functions; these automatically log into the current cpu's channel
19 are associated with the channel buffers using the API described below.
21 The format of the data logged into the channel buffers is completely
25 filtering - this also is left to the kernel client. The purpose is to
30 functions in the relay interface code - please see that for details.
[all …]
/linux-6.14.4/include/linux/platform_data/
Ddma-dw.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 2010-2011 ST Microelectronics
22 * struct dw_dma_slave - Controller-specific information about a slave
27 * @m_master: memory master for transfers on allocated channel
28 * @p_master: peripheral master for transfers on allocated channel
43 * struct dw_dma_platform_data - Controller configuration parameters
47 * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
49 * @data_width: Maximum data width supported by hardware per AHB master
51 * @multi_block: Multi block transfers supported by hardware per channel.
53 * per channel (in units of CTL.SRC_TR_WIDTH/CTL.DST_TR_WIDTH).
[all …]
/linux-6.14.4/drivers/slimbus/
Dslimbus.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2011-2017, The Linux Foundation
14 /* Standard values per SLIMbus spec needed by controllers and devices */
48 /* Data channel management messages */
64 /* Clock pause values per SLIMbus spec */
74 /* Standard values per SLIMbus spec needed by controllers and devices */
82 /* Standard values per SLIMbus spec needed by controllers and devices */
86 /* Manager's logical address is set to 0xFF per spec */
91 * struct slim_framer - Represents SLIMbus framer.
94 * Manager is responsible for framer hand-over.
[all …]
/linux-6.14.4/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
Dfwil_types.h1 // SPDX-License-Identifier: ISC
38 #define BRCMF_STA_SCBSTATS 0x00004000 /* Per STA debug stats */
56 /* masks for channel and ssid count */
79 #define BRCMF_OBSS_COEX_AUTO (-1)
88 /* Wakeup on loss-of-link due to Disassoc/Deauth: */
98 /* Wakeup after receipt of EAP-Identity Req: */
237 __le32 channel; member
255 * struct tdls_iovar - common structure for tdls iovars.
259 * @chanspec: channel specification.
337 u8 ctl_ch; /* 802.11N BSS control channel number */
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/linux-6.14.4/Documentation/devicetree/bindings/dma/xilinx/
Dxilinx_dma.txt2 It can be configured to have one channel or two channels. If configured
7 target devices. It can be configured to have one channel or two channels.
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
19 - compatible: Should be one of-
20 "xlnx,axi-vdma-1.00.a"
21 "xlnx,axi-dma-1.00.a"
22 "xlnx,axi-cdma-1.00.a"
23 "xlnx,axi-mcdma-1.00.a"
24 - #dma-cells: Should be <1>, see "dmas" property below
[all …]
/linux-6.14.4/drivers/net/wireless/intel/iwlwifi/fw/api/
Dtdls.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018, 2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
11 #include "fw/api/phy-ctxt.h"
23 * struct iwl_tdls_channel_switch_timing - Switch timing in TDLS channel-switch
24 * @frame_timestamp: GP2 timestamp of channel-switch request/response packet
27 * to the TDLS off-channel communication. For instance if the DTIM is
30 * @switch_time: switch time the peer sent in its channel switch timing IE
31 * @switch_timeout: switch timeout the peer sent in its channel switch timing IE
[all …]
Dscan.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
13 * enum iwl_scan_subcmd_ids - scan commands
33 * struct iwl_ssid_ie - directed scan network information element
37 * each channel may select different ssids from among the 20 entries.
78 * struct iwl_scan_offload_blocklist - SCAN_OFFLOAD_BLACKLIST_S
81 * @client_bitmap: clients ignore this entry - enum scan_framework_client
112 * struct iwl_scan_offload_profile - SCAN_OFFLOAD_PROFILE_S
[all …]
Dnvm-reg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
11 * enum iwl_regulatory_and_nvm_subcmd_ids - regulatory/NVM commands
61 * enum iwl_nvm_access_op - NVM access opcode
71 * enum iwl_nvm_access_target - target of the NVM_ACCESS_CMD
83 * enum iwl_nvm_section_type - section types for NVM_ACCESS_CMD
105 * struct iwl_nvm_access_cmd - Request the device to send an NVM section
123 * struct iwl_nvm_access_resp - response to NVM_ACCESS_CMD
[all …]
Dlocation.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2015-2017 Intel Deutschland GmbH
4 * Copyright (C) 2018-2022 Intel Corporation
11 * enum iwl_location_subcmd_ids - location group command IDs
86 * struct iwl_tof_config_cmd - ToF configuration
88 * @one_sided_disabled: indicates if one-sided is disabled (or not)
90 * @is_buf_required: indicates if channel estimation buffer is required
100 * enum iwl_tof_bandwidth - values for iwl_tof_range_req_ap_entry.bandwidth
101 * @IWL_TOF_BW_20_LEGACY: 20 MHz non-HT
118 * enum iwl_tof_algo_type - Algorithym type for range measurement request
[all …]
/linux-6.14.4/include/sound/sof/
Dchannel_map.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
16 * \brief Channel map, specifies transformation of one-to-many or many-to-one.
18 * In case of one-to-many specifies how the output channels are computed out of
19 * a single source channel,
20 * in case of many-to-one specifies how a single target channel is computed
23 * Channel index specifies position of the channel in the stream on the 'one'
29 * Channel mask describes which channels are taken into account on the "many"
30 * side. Bit[i] set to 1 means that i-th channel is used for computation
33 * Channel mask is followed by array of coefficients in Q2.30 format,
34 * one per each channel set in the mask (left to right, LS bit set in the
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Damd-xgbe.txt1 * AMD 10GbE driver (amd-xgbe)
4 - compatible: Should be "amd,xgbe-seattle-v1a"
5 - reg: Address and length of the register sets for the device
6 - MAC registers
7 - PCS registers
8 - SerDes Rx/Tx registers
9 - SerDes integration registers (1/2)
10 - SerDes integration registers (2/2)
11 - interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt
13 amd,per-channel-interrupt property is specified, then one additional
[all …]
/linux-6.14.4/sound/firewire/dice/
Ddice-interface.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * block read transactions with at least quadlet-aligned offset and length.
12 * Writes are not allowed except where noted; quadlet-sized registers must be
15 * All values are in big endian. The DICE firmware runs on a little-endian CPU
16 * and just byte-swaps _all_ quadlets on the bus, so values without endianness
17 * (e.g. strings) get scrambled and must be byte-swapped again by the driver.
32 * size values are measured in quadlets. Read-only.
50 * Stores the full 64-bit address (node ID and offset in the node's address
60 * A bitmask with asynchronous events; read-only. When any event(s) happen,
74 /* Other bits may be used for device-specific events. */
[all …]
/linux-6.14.4/drivers/staging/media/atomisp/include/linux/
Datomisp_platform.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 #include <media/v4l2-subdev.h>
39 ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY,/* 8 bits per subpixel (legacy) */
40 ATOMISP_INPUT_FORMAT_YUV420_8, /* 8 bits per subpixel */
41 ATOMISP_INPUT_FORMAT_YUV420_10,/* 10 bits per subpixel */
42 ATOMISP_INPUT_FORMAT_YUV420_16,/* 16 bits per subpixel */
43 ATOMISP_INPUT_FORMAT_YUV422_8, /* UYVY..UVYV, 8 bits per subpixel */
44 ATOMISP_INPUT_FORMAT_YUV422_10,/* UYVY..UVYV, 10 bits per subpixel */
45 ATOMISP_INPUT_FORMAT_YUV422_16,/* UYVY..UVYV, 16 bits per subpixel */
46 ATOMISP_INPUT_FORMAT_RGB_444, /* BGR..BGR, 4 bits per subpixel */
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/dma/
Dsnps,dma-spear1340.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <[email protected]>
11 - Andy Shevchenko <[email protected]>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
21 - enum:
[all …]
/linux-6.14.4/drivers/video/fbdev/
Dpxa3xx-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 #define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */
21 #define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */
22 #define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */
23 #define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */
24 #define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */
25 #define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */
26 #define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */
49 #define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
50 #define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */
[all …]
/linux-6.14.4/sound/pci/emu10k1/
Dp16v.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) by James Courtier-Dutton <[email protected]>
11 /* Audigy2 P16V pointer-offset register set, accessed through the PTR2 and DATA2 registers …
25 #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
41 /* [0:1] Capture input 0 channel select. 0 = Capture output 0.
45 * [3:2] Capture input 1 channel select. 0 = Capture output 0.
49 * [5:4] Capture input 2 channel select. 0 = Capture output 0.
53 * [7:6] Capture input 3 channel select. 0 = Capture output 0.
57 * [9:8] Playback input 0 channel select. 0 = Play output 0.
61 * [11:10] Playback input 1 channel select. 0 = Play output 0.
[all …]
/linux-6.14.4/drivers/misc/
Dhpilo.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
16 /* max number of open channel control blocks per device, hw limited to 32 */
18 /* min number of open channel control blocks per device, hw limited to 32 */
26 /* per spin wait time in usec */
32 * Per device, used to track global memory allocations.
41 /* shared memory on device used for channel control blocks */
52 * -> alloc_lock used when adding/removing/searching ccb_alloc,
54 * --> fifo_lock controls access to fifo queues shared with hw
75 * Channel control block. Used to manage hardware queues.
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