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/linux-6.14.4/Documentation/devicetree/bindings/media/
Dbrcm,bcm2835-unicam.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/brcm,bcm2835-unicam.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Raspberry Pi Kernel Maintenance <kernel-[email protected]>
12 description: |-
14 CSI-2 or CCP2 data from image sensors or similar devices.
26 const: brcm,bcm2835-unicam
30 - description: Unicam block.
31 - description: Clock Manager Image (CMI) block.
[all …]
/linux-6.14.4/arch/arm64/boot/dts/rockchip/
Drk3568-nanopi-r5s.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
9 /dts-v1/;
10 #include "rk3568-nanopi-r5s.dtsi"
14 compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
20 gpio-leds {
21 compatible = "gpio-leds";
22 pinctrl-names = "default";
23 pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;
25 led-lan1 {
28 function-enumerator = <1>;
[all …]
Drk3568-radxa-e25.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include "rk3568-radxa-cm3i.dtsi"
14 pwm-leds {
15 compatible = "pwm-leds-multicolor";
17 multi-led {
20 max-brightness = <255>;
22 led-red {
27 led-green {
32 led-blue {
[all …]
Drk3588-friendlyelec-cm3588-nas.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/rockchip.h>
14 #include <dt-bindings/soc/rockchip,vop2.h>
15 #include <dt-bindings/usb/pd.h>
16 #include "rk3588-friendlyelec-cm3588.dtsi"
20 compatible = "friendlyarm,cm3588-nas", "friendlyarm,cm3588", "rockchip,rk3588";
22 adc_key_recovery: adc-key-recovery {
[all …]
Drk3568-fastrhino-r66s.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 /dts-v1/;
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/soc/rockchip,vop2.h>
13 stdout-path = "serial2:1500000n8";
16 gpio-keys {
17 compatible = "gpio-keys";
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/pci/
Dsamsung,exynos-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Szyprowski <[email protected]>
11 - Jaehoon Chung <[email protected]>
16 snps,dw-pcie.yaml.
19 - $ref: /schemas/pci/snps,dw-pcie.yaml#
23 const: samsung,exynos5433-pcie
27 - description: Data Bus Interface (DBI) registers.
[all …]
Dtoshiba,visconti-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/toshiba,visconti-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nobuhiro Iwamatsu <[email protected]>
16 - $ref: /schemas/pci/snps,dw-pcie.yaml#
20 const: toshiba,visconti-pcie
24 - description: Data Bus Interface (DBI) registers.
25 - description: PCIe configuration space region.
26 - description: Visconti specific additional registers.
[all …]
Dsnps,dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <[email protected]>
11 - Gustavo Pimentel <[email protected]>
22 DWC PCIe CSR space is normally accessed over the dedicated Data Bus
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
[all …]
Drockchip-dw-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Niklas Cassel <[email protected]>
15 snps,dw-pcie-ep.yaml.
18 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
19 - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
24 - rockchip,rk3568-pcie-ep
25 - rockchip,rk3588-pcie-ep
[all …]
/linux-6.14.4/drivers/pci/controller/cadence/
Dpci-j721e.c1 // SPDX-License-Identifier: GPL-2.0
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
10 #include <linux/clk-provider.h>
25 #include "pcie-cadence.h"
83 return readl(pcie->user_cfg_base + offset); in j721e_pcie_user_readl()
89 writel(value, pcie->user_cfg_base + offset); in j721e_pcie_user_writel()
94 return readl(pcie->intd_cfg_base + offset); in j721e_pcie_intd_readl()
100 writel(value, pcie->intd_cfg_base + offset); in j721e_pcie_intd_writel()
106 struct device *dev = pcie->cdns_pcie->dev; in j721e_pcie_link_irq_handler()
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/include/
Damd_acpi.h48 u8 thermal_state; /* thermal state: state id (0: exit state, non-0: state) */
52 u8 backlight_level; /* panel backlight level (0-255) */
64 u8 ipnut_signal; /* input signal in range 0-255 */
73 u8 min_input_signal; /* max input signal in range 0-255 */
74 u8 max_input_signal; /* min input signal in range 0-255 */
75 u8 number_of_points; /* number of data points */
94 u16 client_id; /* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */
108 u16 dgpu_id; /* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */
136 * ARG0: (ACPI_INTEGER) offset of vbios rom data
154 * WORD - structure size in bytes (includes size field)
[all …]
/linux-6.14.4/drivers/phy/qualcomm/
Dphy-qcom-qmp-ufs.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
24 #include "phy-qcom-qmp-common.h"
26 #include "phy-qcom-qmp.h"
27 #include "phy-qcom-qmp-pcs-ufs-v2.h"
28 #include "phy-qcom-qmp-pcs-ufs-v3.h"
29 #include "phy-qcom-qmp-pcs-ufs-v4.h"
30 #include "phy-qcom-qmp-pcs-ufs-v5.h"
31 #include "phy-qcom-qmp-pcs-ufs-v6.h"
33 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
[all …]
/linux-6.14.4/drivers/acpi/
Dmipi-disco-img.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Support MIPI DisCo for Imaging by parsing ACPI _CRS CSI-2 records defined in
8 * Section 6.4.3.8.2.4 "Camera Serial Interface (CSI-2) Connection Resource
12 * The implementation looks for the information in the ACPI namespace (CSI-2
14 * Documentation/firmware-guide/acpi/dsd/graph.rst to represent the CSI-2
15 * connection graph. The software nodes are then populated with the data
16 * extracted from the _CRS CSI-2 resource descriptors and the MIPI DisCo
18 * with CSI-2 connections.
31 #include <media/v4l2-fwnode.h>
41 /* Connection data extracted from one _CRS CSI-2 resource descriptor. */
[all …]
/linux-6.14.4/arch/arm64/boot/dts/freescale/
Dimx8mm-evk.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9 #include <dt-bindings/usb/pd.h>
14 stdout-path = &uart2;
22 hdmi-connector {
23 compatible = "hdmi-connector";
29 remote-endpoint = <&adv7535_out>;
35 compatible = "gpio-leds";
36 pinctrl-names = "default";
[all …]
/linux-6.14.4/drivers/phy/rockchip/
Dphy-rockchip-inno-csidphy.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/phy/phy-mipi-dphy.h>
60 /* Configure the count time of the THS-SETTLE by protocol. */
71 * The higher 16-bit of this register is used for write protection
93 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
145 const struct dphy_drv_data *drv_data = priv->drv_data; in write_grf_reg()
146 const struct dphy_reg *reg = &drv_data->grf_regs[index]; in write_grf_reg()
148 if (reg->offset) in write_grf_reg()
149 regmap_write(priv->grf, reg->offset, in write_grf_reg()
150 HIWORD_UPDATE(value, reg->mask, reg->shift)); in write_grf_reg()
[all …]
/linux-6.14.4/drivers/gpu/drm/bridge/
Dsii902x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Boris Brezillon <boris.brezillon@free-electrons.com>
12 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
16 #include <linux/i2c-mux.h>
18 #include <linux/media-bus-format.h>
31 #include <sound/hdmi-codec.h>
160 (SII902X_TPI_MISC_INFOFRAME_END - SII902X_TPI_MISC_INFOFRAME_BASE)
199 union i2c_smbus_data data; in sii902x_read_unlocked() local
202 ret = __i2c_smbus_xfer(i2c->adapter, i2c->addr, i2c->flags, in sii902x_read_unlocked()
203 I2C_SMBUS_READ, reg, I2C_SMBUS_BYTE_DATA, &data); in sii902x_read_unlocked()
[all …]
Dlontium-lt8912b.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/media-bus-format.h>
89 return regmap_multi_reg_write(lt->regmap[I2C_MAIN], seq, ARRAY_SIZE(seq)); in lt8912_write_init_config()
102 return regmap_multi_reg_write(lt->regmap[I2C_CEC_DSI], seq, ARRAY_SIZE(seq)); in lt8912_write_mipi_basic_config()
155 return regmap_multi_reg_write(lt->regmap[I2C_CEC_DSI], seq, ARRAY_SIZE(seq)); in lt8912_write_dds_config()
162 ret = regmap_write(lt->regmap[I2C_MAIN], 0x03, 0x7f); in lt8912_write_rxlogicres_config()
164 ret |= regmap_write(lt->regmap[I2C_MAIN], 0x03, 0xff); in lt8912_write_rxlogicres_config()
180 {0x52, 0x04}, // loopdiv=0, use second-order PLL in lt8912_write_lvds_config()
200 return regmap_multi_reg_write(lt->regmap[I2C_MAIN], seq, ARRAY_SIZE(seq)); in lt8912_write_lvds_config()
232 return -ENODEV; in lt8912_init_i2c()
[all …]
/linux-6.14.4/drivers/gpu/drm/tegra/
Dsor.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
488 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl()
490 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
498 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
499 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
506 clk_disable_unprepare(sor->clk); in tegra_sor_set_parent_clock()
508 err = clk_set_parent(sor->clk_out, parent); in tegra_sor_set_parent_clock()
512 err = clk_prepare_enable(sor->clk); in tegra_sor_set_parent_clock()
535 * Implementing ->set_parent() here isn't really required because the parent
[all …]
/linux-6.14.4/arch/arm/boot/dts/axis/
Dartpec6.dtsi2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
[all …]
/linux-6.14.4/drivers/staging/media/tegra-video/
Dcsi.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <media/v4l2-fwnode.h>
70 return -ENOIOCTLCMD; in csi_enum_bus_code()
72 if (code->index >= ARRAY_SIZE(tegra_csi_tpg_fmts)) in csi_enum_bus_code()
73 return -EINVAL; in csi_enum_bus_code()
75 code->code = tegra_csi_tpg_fmts[code->index].code; in csi_enum_bus_code()
87 return -ENOIOCTLCMD; in csi_get_format()
89 fmt->format = csi_chan->format; in csi_get_format()
100 frmrate = csi->soc->tpg_frmrate_table; in csi_get_frmrate_table_index()
101 for (i = 0; i < csi->soc->tpg_frmrate_table_size; i++) { in csi_get_frmrate_table_index()
[all …]
/linux-6.14.4/arch/arm/boot/dts/ti/omap/
Ddra72-evm-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "dra7-ipu-dsp-common.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/clock/ti-dra7-atl.h>
13 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
20 stdout-path = &uart1;
23 evm_12v0: fixedregulator-evm12v0 {
25 compatible = "regulator-fixed";
[all …]
/linux-6.14.4/Documentation/ABI/stable/
Dsysfs-class-infiniband2 -------------------------------------------------
9 Contact: linux-[email protected]
24 Contact: linux-[email protected]
34 Contact: linux-[email protected]
39 What: /sys/class/infiniband/<device>/ports/<port-num>/lid
40 What: /sys/class/infiniband/<device>/ports/<port-num>/rate
41 What: /sys/class/infiniband/<device>/ports/<port-num>/lid_mask_count
42 What: /sys/class/infiniband/<device>/ports/<port-num>/sm_sl
43 What: /sys/class/infiniband/<device>/ports/<port-num>/sm_lid
44 What: /sys/class/infiniband/<device>/ports/<port-num>/state
[all …]
/linux-6.14.4/drivers/net/dsa/b53/
Db53_srab.c4 * Copyright (C) 2013 Hauke Mehrtens <hauke@hauke-m.de>
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
38 /* high order word of write data to switch registe */
41 /* low order word of write data to switch registe */
44 /* high order word of read data from switch register */
47 /* low order word of read data from switch register */
81 unsigned int num; member
93 struct b53_srab_priv *priv = dev->priv; in b53_srab_request_grant()
94 u8 __iomem *regs = priv->regs; in b53_srab_request_grant()
109 return -EIO; in b53_srab_request_grant()
[all …]
/linux-6.14.4/drivers/phy/mediatek/
Dphy-mtk-mipi-csi-0-5.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/phy/phy.h>
19 #include "phy-mtk-io.h"
20 #include "phy-mtk-mipi-csi-0-5-rx-reg.h"
76 void __iomem *base = port->base; in mtk_mipi_phy_power_on()
79 * The driver currently supports DPHY and CD-PHY phys, in mtk_mipi_phy_power_on()
81 * so CD-PHY capable phys must be configured in DPHY mode in mtk_mipi_phy_power_on()
83 if (port->type == CDPHY) { in mtk_mipi_phy_power_on()
92 * Only 4 data + 1 clock is supported for now with the following mapping: in mtk_mipi_phy_power_on()
94 * CSIXA_LNR0 --> D2 in mtk_mipi_phy_power_on()
[all …]
/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dsa8295p-adp.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
11 #include <dt-bindings/spmi/spmi.h>
12 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
15 #include "sa8540p-pmics.dtsi"
19 compatible = "qcom,sa8295p-adp", "qcom,sa8540p";
26 stdout-path = "serial0:115200n8";
29 dp2-connector {
[all …]

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