Lines Matching +full:num +full:- +full:data +full:- +full:lanes
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include "rk3568-radxa-cm3i.dtsi"
14 pwm-leds {
15 compatible = "pwm-leds-multicolor";
17 multi-led {
20 max-brightness = <255>;
22 led-red {
27 led-green {
32 led-blue {
39 vbus_typec: regulator-vbus-typec {
40 compatible = "regulator-fixed";
41 enable-active-high;
43 pinctrl-names = "default";
44 pinctrl-0 = <&vbus_typec_en>;
45 regulator-name = "vbus_typec";
46 regulator-min-microvolt = <5000000>;
47 regulator-max-microvolt = <5000000>;
48 vin-supply = <&vcc5v0_sys>;
54 vcc3v3_minipcie: regulator-vcc3v3-minipcie {
55 compatible = "regulator-fixed";
56 enable-active-high;
58 pinctrl-names = "default";
59 pinctrl-0 = <&minipcie_enable_h>;
60 regulator-name = "vcc3v3_minipcie";
61 regulator-min-microvolt = <3300000>;
62 regulator-max-microvolt = <3300000>;
63 vin-supply = <&vcc3v3_pi6c_05>;
66 vcc3v3_ngff: regulator-vcc3v3-ngff {
67 compatible = "regulator-fixed";
68 enable-active-high;
70 pinctrl-names = "default";
71 pinctrl-0 = <&ngffpcie_enable_h>;
72 regulator-name = "vcc3v3_ngff";
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
75 vin-supply = <&vcc5v0_sys>;
78 vcc3v3_pcie30x1: regulator-vcc3v3-pcie30x1 {
79 compatible = "regulator-fixed";
80 enable-active-high;
82 pinctrl-names = "default";
83 pinctrl-0 = <&pcie30x1_enable_h>;
84 regulator-name = "vcc3v3_pcie30x1";
85 regulator-min-microvolt = <3300000>;
86 regulator-max-microvolt = <3300000>;
87 vin-supply = <&vcc5v0_sys>;
90 vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 {
91 compatible = "regulator-fixed";
92 enable-active-high;
94 pinctrl-names = "default";
95 pinctrl-0 = <&pcie_enable_h>;
96 regulator-name = "vcc3v3_pcie";
97 regulator-min-microvolt = <3300000>;
98 regulator-max-microvolt = <3300000>;
99 vin-supply = <&vcc5v0_sys>;
104 phy-supply = <&vcc3v3_pcie30x1>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pcie20_reset_h>;
114 reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
115 vpcie3v3-supply = <&vcc3v3_pi6c_05>;
120 data-lanes = <1 2>;
125 num-lanes = <1>;
126 pinctrl-names = "default";
127 pinctrl-0 = <&pcie30x1_reset_h>;
128 reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
129 vpcie3v3-supply = <&vcc3v3_minipcie>;
134 num-lanes = <1>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pcie30x2_reset_h>;
137 reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
138 vpcie3v3-supply = <&vcc3v3_pi6c_05>;
144 pcie20_reset_h: pcie20-reset-h {
148 pcie30x1_enable_h: pcie30x1-enable-h {
152 pcie30x1_reset_h: pcie30x1-reset-h {
156 pcie30x2_reset_h: pcie30x2-reset-h {
160 pcie_enable_h: pcie-enable-h {
166 minipcie_enable_h: minipcie-enable-h {
170 ngffpcie_enable_h: ngffpcie-enable-h {
189 pinctrl-names = "default";
190 pinctrl-0 = <&pwm12m1_pins>;
199 bus-width = <4>;
200 cap-sd-highspeed;
201 cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
203 disable-wp;
204 pinctrl-names = "default";
205 pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
206 sd-uhs-sdr104;
207 vmmc-supply = <&vcc3v3_sd>;
208 vqmmc-supply = <&vccio_sd>;
233 phy-supply = <&vbus_typec>;
238 phy-supply = <&vcc3v3_minipcie>;
243 phy-supply = <&vcc3v3_ngff>;