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/linux-6.14.4/Documentation/devicetree/bindings/mailbox/
Darm,mhu.yaml99 interrupts = <0 36 4>, /* LP-NonSecure */
100 <0 35 4>, /* HP-NonSecure */
110 mboxes = <&mhuA 1>; /* HP-NonSecure */
111 shmem = <&cpu_scp_hpri>; /* HP-NonSecure */
131 interrupts = <0 36 4>, /* LP-NonSecure */
132 <0 35 4>, /* HP-NonSecure */
142 mboxes = <&mhuB 0 0>, /* LP-NonSecure, 1st doorbell */
143 <&mhuB 0 1>; /* LP-NonSecure, 2nd doorbell */
160 mboxes = <&mhuB 1 2>, /* HP-NonSecure, 3rd doorbell */
161 <&mhuB 1 3>; /* HP-NonSecure, 4th doorbell */
/linux-6.14.4/tools/arch/arm/include/uapi/asm/
Dkvm.h154 * For KVM currently all guest registers are nonsecure, but we reserve a bit
155 * in the encoding to distinguish secure from nonsecure for AArch32 system
157 * register, and 0 for the nonsecure banked register or if the register is
/linux-6.14.4/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra194-cbb.yaml59 CCPLEX receives secure or nonsecure interrupt depending on error type.
/linux-6.14.4/Documentation/devicetree/bindings/firmware/
Darm,scpi.yaml178 shmem = <&cpu_scp_hpri>; /* HP-NonSecure */
/linux-6.14.4/drivers/hwtracing/coresight/
Dcoresight-etm4x.h706 #define ETM_EXLEVEL_NS_APP BIT(4) /* NonSecure EL0 */
707 #define ETM_EXLEVEL_NS_OS BIT(5) /* NonSecure EL1 */
708 #define ETM_EXLEVEL_NS_HYP BIT(6) /* NonSecure EL2 */
Dcoresight-etm4x-core.c1456 * EXLEVEL_NS, for NonSecure Exception levels. in etm4_get_ns_access_type()
/linux-6.14.4/drivers/dma/
Dpl330.c305 bool nonsecure; member
1036 ns = desc->rqcfg.nonsecure ? 1 : 0; in _trigger()
1450 if (rqc->nonsecure) in _prepare_ccr()
1523 desc->rqcfg.nonsecure = 0; in pl330_submit_req()
1525 desc->rqcfg.nonsecure = 1; in pl330_submit_req()
/linux-6.14.4/arch/arm/boot/dts/ti/omap/
Domap5.dtsi95 /* PPI secure/nonsecure IRQ */