| /aosp_15_r20/external/pytorch/torch/backends/xeon/ |
| H A D | run_cpu.py | 1 # mypy: allow-untyped-defs
5 Single instance inference, multi-instance inference are enabled.
15 +-----------------------------+----------------------+-------+
20 | +----------------------+-------+
23 | +----------------------+-------+
25 | +----------------------+-------+
28 +-----------------------------+----------------------+-------+
36 +------------------+-------------------------------------------------------------------------------…
41 +------------------+-------------------------------------------------------------------------------…
43 +------------------+-------------------------------------------------------------------------------…
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| /aosp_15_r20/external/trusty/arm-trusted-firmware/docs/plat/ |
| D | nvidia-tegra.rst | 4 - .. rubric:: T194
7 T194 has eight NVIDIA Carmel CPU cores in a coherent multi-processor
8 configuration. The Carmel cores support the ARM Architecture version 8.2,
9 executing both 64-bit AArch64 code, and 32-bit AArch32 code. The Carmel
10 processors are organized as four dual-core clusters, where each cluster has
11 a dedicated 2 MiB Level-2 unified cache. A high speed coherency fabric connects
12 these processor complexes and allows heterogeneous multi-processing with all
13 eight cores if required.
15 - .. rubric:: T186
18 The NVIDIA® Parker (T186) series system-on-chip (SoC) delivers a heterogeneous
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| /aosp_15_r20/external/arm-trusted-firmware/docs/plat/ |
| H A D | nvidia-tegra.rst | 4 - .. rubric:: T194
7 T194 has eight NVIDIA Carmel CPU cores in a coherent multi-processor
8 configuration. The Carmel cores support the ARM Architecture version 8.2,
9 executing both 64-bit AArch64 code, and 32-bit AArch32 code. The Carmel
10 processors are organized as four dual-core clusters, where each cluster has
11 a dedicated 2 MiB Level-2 unified cache. A high speed coherency fabric connects
12 these processor complexes and allows heterogeneous multi-processing with all
13 eight cores if required.
15 - .. rubric:: T186
18 The NVIDIA® Parker (T186) series system-on-chip (SoC) delivers a heterogeneous
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|
| H A D | rpi3.rst | 4 The `Raspberry Pi 3`_ is an inexpensive single-board computer that contains four
5 Arm Cortex-A53 cores.
7 The following instructions explain how to use this port of the TF-A with the
11 port of TF-A can't boot a AArch64 kernel. The `Linux tree fork`_ maintained by
16 which is available from both the Non-secure and Secure worlds. This port
21 ------
25 card) and is located between all Arm cores and the DRAM. Check the `Raspberry Pi
30 the cores boot in AArch64 mode.
34 - If a file called ``kernel8.img`` is located on the ``boot`` partition of the
38 - If there is also a file called ``armstub8.bin``, it will load it at address
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| /aosp_15_r20/external/eigen/doc/ |
| H A D | TopicMultithreading.dox | 3 /** \page TopicMultiThreading Eigen and multi-threading
7 Some %Eigen's algorithms can exploit the multiple cores present in your hardware.
9 - GCC: \c -fopenmp
10 - ICC: \c -openmp
11 - MSVC: check the respective option in the build properties.
25 You can disable %Eigen's multi threading at compile time by defining the \link TopicPreprocessorDir…
27 Currently, the following algorithms can make use of multi-threading:
28 - general dense matrix - matrix products
29 - PartialPivLU
30 - row-major-sparse * dense vector/matrix products
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| /aosp_15_r20/external/tensorflow/tensorflow/dtensor/python/ |
| H A D | tpu_util.py | 7 # http://www.apache.org/licenses/LICENSE-2.0
15 """TPU-specific utilities for DTensor."""
52 # `_topology.device_coordinates` maps TF task-device ordinals to TPU core IDs.
55 # Cache core ID <-> location mappings so we need not make repeated C++ calls.
56 # Both are indexed by TF task-device ordinals.
96 # User can specify local_device_ids or use default list for multi host.
106 num_devices_per_task: int) -> topology.Topology:
111 and then by per-task device ordinals.
154 calling `dtensor.initialize_multi_client` to initialize multi-client DTensor.
156 variables that controls the initialization of multi-client DTensor.
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| /aosp_15_r20/external/mbedtls/3rdparty/p256-m/p256-m/ |
| H A D | README.md | 1 *This is the original README for the p256-m repository. Please note that as
2 only a subset of p256-m's files are present in Mbed TLS, this README may refer
5 p256-m is a minimalistic implementation of ECDH and ECDSA on NIST P-256,
6 especially suited to constrained 32-bit environments. It's written in standard
7 C, with optional bits of assembly for Arm Cortex-M and Cortex-A CPUs.
16 some might even risk weakening security for more speed. p256-m was written
21 to existing implementations (see below) - in less than 700 LOC.
25 - [Correctness](#correctness)
26 - [Security](#security)
27 - [Code size](#code-size)
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| /aosp_15_r20/external/openthread/third_party/mbedtls/repo/3rdparty/p256-m/p256-m/ |
| H A D | README.md | 1 *This is the original README for the p256-m repository. Please note that as
2 only a subset of p256-m's files are present in Mbed TLS, this README may refer
5 p256-m is a minimalistic implementation of ECDH and ECDSA on NIST P-256,
6 especially suited to constrained 32-bit environments. It's written in standard
7 C, with optional bits of assembly for Arm Cortex-M and Cortex-A CPUs.
16 some might even risk weakening security for more speed. p256-m was written
21 to existing implementations (see below) - in less than 700 LOC.
25 - [Correctness](#correctness)
26 - [Security](#security)
27 - [Code size](#code-size)
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| /aosp_15_r20/external/gemmlowp/internal/ |
| H A D | multi_thread_gemm.h | 7 // http://www.apache.org/licenses/LICENSE-2.0
15 // multi_thread_gemm.h: Multi-threaded GEMM entry point.
31 // This value was empirically derived on an end-to-end application benchmark.
36 // time interval that we might be busy-waiting is very small, so for that
45 // or even turn off the CPU cores that they were running on. That would result
48 // between consecutive GEMM invokations, not just intra-GEMM considerations.
54 // are busy-waiting.
79 // If we can't use NOPs, let's use a non-inline function call as a basic
97 // First does some busy-waiting for a fixed number of no-op cycles,
101 // The idea of doing some initial busy-waiting is to help get
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| /aosp_15_r20/external/coreboot/Documentation/soc/intel/fsp/ppi/ |
| H A D | mp_service_ppi.md | 9 Today coreboot is capable enough to handle multi-processor initialization on IA platforms.
11 The multi-processor initialization code has to take care of lots of duties:
13 1. Bringing all cores out of reset
14 2. Load latest microcode on all cores
29 get-rid of such close source CPU programming.
33 As coreboot is doing CPU multi-processor initialization for IA platform before FSP-S
34 initialization and having all possible information about cores in terms of maximum number
35 of cores, APIC ids, stack size etc. It’s also possible for coreboot to extend its own
46 ```{eval-rst}
47 +------------------------------+------------------------------------------------------------------+
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| /aosp_15_r20/external/cpuinfo/src/x86/ |
| H A D | topology.c | 24 * HTT: indicates multi-core/hyper-threading support on this core. in cpuinfo_x86_detect_topology()
25 * - Intel, AMD: edx[bit 28] in basic info. in cpuinfo_x86_detect_topology()
36 * CmpLegacy: core multi-processing legacy mode. in cpuinfo_x86_detect_topology()
37 * - AMD: ecx[bit 1] in extended info (reserved bit on Intel CPUs). in cpuinfo_x86_detect_topology()
45 * NC: number of physical cores - 1. The number of cores in the processor is NC+1. in cpuinfo_x86_detect_topology()
46 * - AMD: ecx[bits 0-7] in leaf 0x80000008 (reserved zero bits on Intel CPUs). in cpuinfo_x86_detect_topology()
49 topology->core_bits_length = bit_length(cores_per_processor); in cpuinfo_x86_detect_topology()
50 …cpuinfo_log_debug("HTT: APIC ID = %08"PRIx32", cores per processor = %"PRIu32, apic_id, cores_per_… in cpuinfo_x86_detect_topology()
53 * LogicalProcessorCount: the number of cores per processor. in cpuinfo_x86_detect_topology()
54 * - AMD: ebx[bits 16-23] in basic info (different interpretation on Intel CPUs). in cpuinfo_x86_detect_topology()
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| /aosp_15_r20/external/ltp/testcases/kernel/power_management/lib/ |
| H A D | pm_sched_mc.py | 32 os.system('dmesg -c >/dev/null')
69 '''Return 1 if the system is multi socket else return 0
77 print("Failed to check if system is multi socket system")
88 if line.startswith('cpu cores'):
97 print("Failed to check if system is hyper-threaded")
101 ''' Return true if system has sockets has multiple cores
109 if line.startswith('cpu cores'):
127 print("Failed to check if system is multi core system")
140 if line.startswith('cpu cores'):
145 print("Failed to check if system is hyper-threaded")
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/Support/ |
| H A D | Threading.h | 1 //===-- llvm/Support/Threading.h - Control multithreading mode --*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file declares helper functions for running LLVM in a multi-threaded
12 //===----------------------------------------------------------------------===//
19 #include "llvm/Config/llvm-config.h" // for LLVM_ON_UNIX
51 /// Returns true if LLVM is compiled with support for multi-threading, and
129 // threads, or hardware cores.
137 /// multi-socket system, this ensures threads are assigned to all CPU
158 /// based on physical cores, if available for the host system, otherwise falls
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| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/Support/ |
| D | Threading.h | 1 //===-- llvm/Support/Threading.h - Control multithreading mode --*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file declares helper functions for running LLVM in a multi-threaded
12 //===----------------------------------------------------------------------===//
19 #include "llvm/Config/llvm-config.h" // for LLVM_ON_UNIX
51 /// Returns true if LLVM is compiled with support for multi-threading, and
129 // threads, or hardware cores.
137 /// multi-socket system, this ensures threads are assigned to all CPU
158 /// based on physical cores, if available for the host system, otherwise falls
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| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/Support/ |
| D | Threading.h | 1 //===-- llvm/Support/Threading.h - Control multithreading mode --*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file declares helper functions for running LLVM in a multi-threaded
12 //===----------------------------------------------------------------------===//
19 #include "llvm/Config/llvm-config.h" // for LLVM_ON_UNIX
51 /// Returns true if LLVM is compiled with support for multi-threading, and
129 // threads, or hardware cores.
137 /// multi-socket system, this ensures threads are assigned to all CPU
158 /// based on physical cores, if available for the host system, otherwise falls
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| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/Support/ |
| D | Threading.h | 1 //===-- llvm/Support/Threading.h - Control multithreading mode --*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file declares helper functions for running LLVM in a multi-threaded
12 //===----------------------------------------------------------------------===//
19 #include "llvm/Config/llvm-config.h" // for LLVM_ON_UNIX
51 /// Returns true if LLVM is compiled with support for multi-threading, and
129 // threads, or hardware cores.
137 /// multi-socket system, this ensures threads are assigned to all CPU
158 /// based on physical cores, if available for the host system, otherwise falls
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| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/Support/ |
| D | Threading.h | 1 //===-- llvm/Support/Threading.h - Control multithreading mode --*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file declares helper functions for running LLVM in a multi-threaded
12 //===----------------------------------------------------------------------===//
19 #include "llvm/Config/llvm-config.h" // for LLVM_ON_UNIX
51 /// Returns true if LLVM is compiled with support for multi-threading, and
129 // threads, or hardware cores.
137 /// multi-socket system, this ensures threads are assigned to all CPU
158 /// based on physical cores, if available for the host system, otherwise falls
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| /aosp_15_r20/external/tensorflow/tensorflow/python/distribute/cluster_resolver/ |
| H A D | cluster_resolver.py | 7 # http://www.apache.org/licenses/LICENSE-2.0
46 ….append(session._DeviceAttributes(d.name, d.device_type, 0, 0)) # pylint: disable=protected-access
79 In general, multi-client tf.distribute strategies such as
82 the other hand, these concepts are not applicable in single-client strategies,
87 - task_type is the name of the server's current named job (e.g. 'worker',
89 - task_id is the ordinal index of the server within the task type.
90 - rpc_layer is the protocol used by TensorFlow to communicate with other
103 ClusterSpec returned is up-to-date at the time of calling this function.
125 returned is up-to-date at the time to calling this function. This usually
134 """Returns the number of accelerator cores per worker.
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| /aosp_15_r20/external/libpcap/ |
| H A D | pcap-tstamp.manmisc.in | 22 .TH PCAP-TSTAMP @MAN_MISC_INFO@ "14 July 2020"
24 pcap-tstamp \- packet time stamps in libpcap
41 capture device and when the networking stack time-stamps the packet;
48 a high-resolution timer might use a counter that runs at a rate
58 different CPU cores on a multi-core or multi-processor system might be
60 synchronized, so packets time-stamped by different cores might not have
68 the fraction-of-a-second part of the time stamp might roll over past
76 In addition, packets time-stamped by different cores might be
77 time-stamped in one order and added to the queue of packets for libpcap
82 packets; those time stamps are usually high-resolution time stamps, and
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| /aosp_15_r20/external/cpuinfo/src/x86/mach/ |
| H A D | init.c | 8 #include <cpuinfo/internal-api.h>
17 return (UINT32_C(1) << bits) - UINT32_C(1); in bit_mask()
22 struct cpuinfo_core* cores = NULL; in cpuinfo_x86_mach_init() local
38 cores = calloc(mach_topology.cores, sizeof(struct cpuinfo_core)); in cpuinfo_x86_mach_init()
39 if (cores == NULL) { in cpuinfo_x86_mach_init()
40 cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" cores", in cpuinfo_x86_mach_init()
41 mach_topology.cores * sizeof(struct cpuinfo_core), mach_topology.cores); in cpuinfo_x86_mach_init()
44 /* On x86 cluster of cores is a physical package */ in cpuinfo_x86_mach_init()
64 const uint32_t threads_per_core = mach_topology.threads / mach_topology.cores; in cpuinfo_x86_mach_init()
66 const uint32_t cores_per_package = mach_topology.cores / mach_topology.packages; in cpuinfo_x86_mach_init()
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| /aosp_15_r20/external/grpc-grpc/src/python/grpcio_tests/tests/qps/ |
| H A D | worker_server.py | 7 # http://www.apache.org/licenses/LICENSE-2.0
52 return self._end_time - self._start_time
55 return self._utime - self._last_utime
58 return self._stime - self._last_stime
89 # pylint: disable=stop-iteration-return
91 # pylint: enable=stop-iteration-return
93 cores = multiprocessing.cpu_count()
97 yield self._get_server_status(port, cores)
101 status = self._get_server_status(port, cores)
107 def _get_server_status(self, port, cores): argument
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| /aosp_15_r20/frameworks/base/core/tests/coretests/res/xml/ |
| H A D | power_profile_test_cpu_legacy.xml | 1 <?xml version="1.0" encoding="utf-8"?>
2 <!--
9 ~ http://www.apache.org/licenses/LICENSE-2.0
16 -->
18 <!-- All values are in mAh except as noted.
23 -->
25 <!-- This is the battery capacity in mAh -->
28 <!-- Number of cores each CPU cluster contains -->
29 <array name="cpu.clusters.cores">
30 <value>4</value> <!-- Cluster 0 has 4 cores (cpu0, cpu1, cpu2, cpu3) -->
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| /aosp_15_r20/frameworks/base/core/res/res/xml/ |
| H A D | power_profile_test.xml | 1 <?xml version="1.0" encoding="utf-8"?>
2 <!--
10 ** http://www.apache.org/licenses/LICENSE-2.0
18 -->
20 <!-- All values are in mAh except as noted.
25 -->
27 <!-- This is the battery capacity in mAh -->
30 <!-- Number of cores each CPU cluster contains -->
31 <array name="cpu.clusters.cores">
32 <value>4</value> <!-- Cluster 0 has 4 cores (cpu0, cpu1, cpu2, cpu3) -->
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/ |
| H A D | FspsUpd.h | 41 /** FSP-S Configuration
45 /** Offset 0x0020 - PCIe Controller 0 Bifurcation
51 /** Offset 0x0021 - PCIe Controller 1 Bifurcation
57 /** Offset 0x0022 - Active Core Count
58 Select # of Active Cores (Default: 0, 0:ALL, 1..15 = 1..15 Cores)
72 /** Offset 0x002B - PCIe Controller 0
78 /** Offset 0x002C - PCIe Controller 1
84 /** Offset 0x002D - Embedded Multi-Media Controller (eMMC)
85 Enable / Disable Embedded Multi-Media controller
90 /** Offset 0x002E - LAN Controllers
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| /aosp_15_r20/external/coreboot/src/cpu/intel/model_1067x/ |
| H A D | model_1067x_init.c | 1 /* SPDX-License-Identifier: GPL-2.0-only */
26 const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */ in configure_c_states()
67 static void configure_p_states(const char stepping, const char cores) in configure_p_states() argument
77 if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32))) { in configure_p_states()
79 if ((stepping == 0xa) && (cores < 4)) { in configure_p_states()
85 msr.hi &= ~(1 << (32 - 32)); /* Clear turbo disable. */ in configure_p_states()
104 /* Gather p-state information. */ in configure_emttm_tables()
110 --num_states; in configure_emttm_tables()
111 if (pstates.states[pstates.num_states - 1].is_slfm) in configure_emttm_tables()
112 --num_states; in configure_emttm_tables()
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|