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/linux-6.14.4/Documentation/devicetree/bindings/pci/
Dpci-msi.txt2 relationship between PCI devices and MSI controllers.
18 Requester ID. A mechanism is required to associate a device with both the MSI
22 For generic MSI bindings, see
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
30 -------------------
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
36 * rid-base is a single cell describing the first RID matched by the entry.
38 * msi-controller is a single phandle to an MSI controller
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Dxgene-pci-msi.txt1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
8 - reg: physical base address (0x79000000) and length (0x900000) for controller
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
11 - reg-names: not required
12 - interrupts: A list of 16 interrupt outputs of the controller, starting from
14 - interrupt-names: not required
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Dbrcm,iproc-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <[email protected]>
11 - Scott Branden <[email protected]>
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
19 - enum:
22 - brcm,iproc-pcie
23 # for the second generation of PAXB-based controllers, used in
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/linux-6.14.4/drivers/pci/controller/
Dpcie-iproc-msi.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/msi.h>
14 #include "pcie-iproc.h"
18 #define IPROC_MSI_INT_N_EVENT_SHIFT 1
34 /* Size of each MSI address region */
52 * struct iproc_msi_grp - iProc MSI group
54 * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
57 * @msi: pointer to iProc MSI data
62 struct iproc_msi *msi; member
68 * struct iproc_msi - iProc event queue based MSI
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Dpci-xgene-msi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene MSI Driver
13 #include <linux/msi.h>
27 struct xgene_msi *msi; member
48 .name = "X-Gene1 MSI",
62 * X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where
85 * Each index register supports 16 MSI vectors (0..15) to generate interrupt.
86 * There are total 16 GIC IRQs assigned for these 16 groups of MSI termination
89 * Each MSI termination group has 1 MSIINTn register (n is 0..15) to indicate
90 * the MSI pending status caused by 1 of its 8 index registers.
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Dpcie-altera-msi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Altera PCIe MSI support
7 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
15 #include <linux/msi.h>
41 static inline void msi_writel(struct altera_msi *msi, const u32 value, in msi_writel() argument
44 writel_relaxed(value, msi->csr_base + reg); in msi_writel()
47 static inline u32 msi_readl(struct altera_msi *msi, const u32 reg) in msi_readl() argument
49 return readl_relaxed(msi->csr_base + reg); in msi_readl()
55 struct altera_msi *msi; in altera_msi_isr() local
61 msi = irq_desc_get_handler_data(desc); in altera_msi_isr()
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Dpcie-rcar-host.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
16 #include <linux/clk-provider.h>
24 #include <linux/msi.h>
34 #include "pcie-rcar.h"
50 struct rcar_msi msi; member
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Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
20 #include <linux/msi.h>
26 #include <linux/pci-ecam.h>
37 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
165 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
167 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
169 /* MSI target addresses */
182 #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
183 #define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
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/linux-6.14.4/include/linux/
Dmsi.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * This header file contains MSI data structures and functions which are
8 * - Interrupt core code
9 * - PCI/MSI core code
10 * - MSI interrupt domain implementations
11 * - IOMMU, low level VFIO, NTB and other justified exceptions
12 * dealing with low level MSI details.
15 * especially storing MSI descriptor pointers in random code is considered
26 #include <asm/msi.h>
52 * msi_msg - Representation of a MSI message
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/linux-6.14.4/arch/powerpc/sysdev/
Dfsl_msi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
11 #include <linux/msi.h>
24 #include <asm/ppc-pci.h>
39 #define msi_hwirq(msi, msir_index, intr_index) \ argument
40 ((msir_index) << (msi)->srs_shift | \
41 ((intr_index) << (msi)->ibs_shift))
63 * in the cascade interrupt. So, this MSI interrupt has been acked
71 struct fsl_msi *msi_data = irqd->domain->host_data; in fsl_msi_print_chip()
75 srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK; in fsl_msi_print_chip()
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/linux-6.14.4/Documentation/devicetree/bindings/interrupt-controller/
Dmsi.txt1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
14 - The doorbell (the MMIO address written to).
17 they can address. An MSI controller may feature a number of doorbells.
19 - The payload (the value written to the doorbell).
22 MSI controllers may have restrictions on permitted payloads.
24 - Sideband information accompanying the write.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
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Dfsl,ls-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Layerscape SCFG PCIe MSI controller
11 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
12 platforms. If interrupt-parent is not provided, the default parent interrupt
15 Each PCIe node needs to have property msi-parent that points to
16 MSI controller node
19 - Frank Li <[email protected]>
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Dloongson,pch-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson PCH MSI Controller
10 - Jiaxun Yang <[email protected]>
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
22 maxItems: 1
24 loongson,msi-base-vec:
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Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <[email protected]>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
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Dfsl,mu-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
10 - Frank Li <[email protected]>
23 registers (Processor A-side, Processor B-side).
25 MU can work as msi interrupt controller to do doorbell
28 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
33 - fsl,imx6sx-mu-msi
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/linux-6.14.4/Documentation/PCI/
Dmsi-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
5 The MSI Driver Guide HOWTO
16 the advantages of using MSI over traditional interrupt mechanisms, how
17 to change your driver to use MSI or MSI-X and some basic diagnostics to
27 The MSI capability was first specified in PCI 2.2 and was later enhanced
28 in PCI 3.0 to allow each interrupt to be masked individually. The MSI-X
30 per device than MSI and allows interrupts to be independently configured.
32 Devices may support both MSI and MSI-X, but only one can be enabled at
40 traditional pin-based interrupts.
42 Pin-based PCI interrupts are often shared amongst several devices.
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/linux-6.14.4/drivers/pci/msi/
Dapi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI MSI/MSI-X — Exported APIs for device drivers
5 * Copyright (C) 2003-2004 Intel
14 #include "msi.h"
17 * pci_enable_msi() - Enable MSI interrupt mode on device
20 * Legacy device driver API to enable MSI interrupts mode on device and
22 * Linux IRQ will be saved at @dev->irq. The driver must invoke
32 int rc = __pci_enable_msi_range(dev, 1, 1, NULL); in pci_enable_msi()
40 * pci_disable_msi() - Disable MSI interrupt mode on device
43 * Legacy device driver API to disable MSI interrupt mode on device,
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Dmsi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
15 #include "msi.h"
17 int pci_msi_enable = 1;
21 * pci_msi_supported - check whether MSI may be enabled on a device
22 * @dev: pointer to the pci_dev data structure of MSI device function
26 * to determine if MSI/-X are supported for the device. If MSI/-X is
27 * supported return 1, else return 0.
33 /* MSI must be globally enabled and supported by the device */ in pci_msi_supported()
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/linux-6.14.4/arch/mips/pci/
Dmsi-octeon.c6 * Copyright (C) 2005-2009, 2010 Cavium Networks
10 #include <linux/msi.h>
15 #include <asm/octeon/cvmx-npi-defs.h>
16 #include <asm/octeon/cvmx-pci-defs.h>
17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-sli-defs.h>
19 #include <asm/octeon/cvmx-pexp-defs.h>
20 #include <asm/octeon/pci-octeon.h>
23 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
31 * is used so we can disable all of the MSI interrupts when a device
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/linux-6.14.4/drivers/pci/controller/mobiveil/
Dpcie-mobiveil-host.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright 2019-2020 NXP
19 #include <linux/msi.h>
25 #include "pcie-mobiveil.h"
37 if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0)) in mobiveil_pcie_valid_device()
44 * mobiveil_pcie_map_bus - routine to get the configuration base of either
50 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus()
51 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
59 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
67 value = bus->number << PAB_BUS_SHIFT | in mobiveil_pcie_map_bus()
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/linux-6.14.4/arch/arm64/kvm/vgic/
Dvgic-irqfd.c1 // SPDX-License-Identifier: GPL-2.0-only
22 unsigned int spi_id = e->irqchip.pin + VGIC_NR_PRIVATE_IRQS; in vgic_irqfd_set_irq()
25 return -EINVAL; in vgic_irqfd_set_irq()
36 * return 0 on success, -EINVAL on errors.
42 int r = -EINVAL; in kvm_set_routing_entry()
44 switch (ue->type) { in kvm_set_routing_entry()
46 e->set = vgic_irqfd_set_irq; in kvm_set_routing_entry()
47 e->irqchip.irqchip = ue->u.irqchip.irqchip; in kvm_set_routing_entry()
48 e->irqchip.pin = ue->u.irqchip.pin; in kvm_set_routing_entry()
49 if ((e->irqchip.pin >= KVM_IRQCHIP_NUM_PINS) || in kvm_set_routing_entry()
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/linux-6.14.4/kernel/irq/
Dmsi.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/msi.h>
25 * struct msi_device_data - MSI per device data
26 * @properties: MSI properties which are interesting to drivers
27 * @mutex: Mutex protecting the MSI descriptor store
28 * @__domains: Internal data for per device MSI domains
39 * struct msi_ctrl - MSI internal management control structure
44 * than the range due to PCI/multi-MSI.
54 #define MSI_XA_MAX_INDEX (ULONG_MAX - 1)
56 #define MSI_XA_DOMAIN_SIZE (MSI_MAX_INDEX + 1)
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/linux-6.14.4/drivers/irqchip/
Dirq-msi-lib.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "irq-msi-lib.h"
10 * msi_lib_init_dev_msi_info - Domain info setup for MSI domains
18 * This function is to be used for all types of MSI domains above the root
30 const struct msi_parent_ops *pops = real_parent->msi_parent_ops; in msi_lib_init_dev_msi_info()
38 * MSI parent domain specific settings. For now there is only the in msi_lib_init_dev_msi_info()
39 * root parent domain, e.g. NEXUS, acting as a MSI parent, but it is in msi_lib_init_dev_msi_info()
40 * possible to stack MSI parents. See x86 vector -> irq remapping in msi_lib_init_dev_msi_info()
42 if (domain->bus_token == pops->bus_select_token) { in msi_lib_init_dev_msi_info()
46 WARN_ON_ONCE(1); in msi_lib_init_dev_msi_info()
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/linux-6.14.4/Documentation/devicetree/bindings/misc/
Dfsl,qoriq-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <[email protected]>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
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/linux-6.14.4/Documentation/devicetree/bindings/bus/
Dfsl,imx8qxp-pixel-link-msi-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
10 - Liu Ying <[email protected]>
13 i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
14 sitting together with the PHYs. It is not the same as the MSI bus coming
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
19 that is, MSI clock and AHB clock, need to be enabled so that peripherals
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