Lines Matching +full:msi +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
20 #include <linux/msi.h>
26 #include <linux/pci-ecam.h>
37 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
165 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
167 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
169 /* MSI target addresses */
182 #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
183 #define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
194 #define IDX_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_INDEX])
195 #define DATA_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_DATA])
196 #define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->reg_offsets[RGR1_SW_INIT_1])
197 #define HARD_DEBUG(pcie) ((pcie)->reg_offsets[PCIE_HARD_DEBUG])
198 #define INTR2_CPU_BASE(pcie) ((pcie)->reg_offsets[PCIE_INTR2_CPU_BASE])
264 int nr; /* No. of MSI available, depends on chip */
278 struct brcm_msi *msi; member
298 return pcie->soc_base == BCM7435 || pcie->soc_base == BCM7425; in is_bmips()
303 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
311 return (log2_in - 12) + 0x1c; in brcm_pcie_encode_ibar_size()
314 return log2_in - 15; in brcm_pcie_encode_ibar_size()
373 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
378 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
383 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_EN_MASK); in brcm_pcie_set_ssc()
384 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_VAL_MASK); in brcm_pcie_set_ssc()
385 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
391 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
399 return ssc && pll ? 0 : -EIO; in brcm_pcie_set_ssc()
402 /* Limits operation to a specific generation (1, 2, or 3) */
405 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
406 u32 lnkcap = readl(pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); in brcm_pcie_set_gen()
409 writel(lnkcap, pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); in brcm_pcie_set_gen()
412 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
425 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win)); in brcm_pcie_set_outbound_win()
426 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win)); in brcm_pcie_set_outbound_win()
430 limit_addr_mb = (cpu_addr + size - 1) / SZ_1M; in brcm_pcie_set_outbound_win()
432 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
437 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
447 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
450 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
453 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
456 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
460 .name = "BRCM STB PCIe MSI",
476 struct brcm_msi *msi; in brcm_pcie_msi_isr() local
481 msi = irq_desc_get_handler_data(desc); in brcm_pcie_msi_isr()
482 dev = msi->dev; in brcm_pcie_msi_isr()
484 status = readl(msi->intr_base + MSI_INT_STATUS); in brcm_pcie_msi_isr()
485 status >>= msi->legacy_shift; in brcm_pcie_msi_isr()
487 for_each_set_bit(bit, &status, msi->nr) { in brcm_pcie_msi_isr()
489 ret = generic_handle_domain_irq(msi->inner_domain, bit); in brcm_pcie_msi_isr()
491 dev_dbg(dev, "unexpected MSI\n"); in brcm_pcie_msi_isr()
499 struct brcm_msi *msi = irq_data_get_irq_chip_data(data); in brcm_msi_compose_msi_msg() local
501 msg->address_lo = lower_32_bits(msi->target_addr); in brcm_msi_compose_msi_msg()
502 msg->address_hi = upper_32_bits(msi->target_addr); in brcm_msi_compose_msi_msg()
503 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq; in brcm_msi_compose_msi_msg()
508 struct brcm_msi *msi = irq_data_get_irq_chip_data(data); in brcm_msi_ack_irq() local
509 const int shift_amt = data->hwirq + msi->legacy_shift; in brcm_msi_ack_irq()
511 writel(1 << shift_amt, msi->intr_base + MSI_INT_CLR); in brcm_msi_ack_irq()
516 .name = "BRCM STB MSI",
521 static int brcm_msi_alloc(struct brcm_msi *msi, unsigned int nr_irqs) in brcm_msi_alloc() argument
525 mutex_lock(&msi->lock); in brcm_msi_alloc()
526 hwirq = bitmap_find_free_region(msi->used, msi->nr, in brcm_msi_alloc()
528 mutex_unlock(&msi->lock); in brcm_msi_alloc()
533 static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq, in brcm_msi_free() argument
536 mutex_lock(&msi->lock); in brcm_msi_free()
537 bitmap_release_region(msi->used, hwirq, order_base_2(nr_irqs)); in brcm_msi_free()
538 mutex_unlock(&msi->lock); in brcm_msi_free()
544 struct brcm_msi *msi = domain->host_data; in brcm_irq_domain_alloc() local
547 hwirq = brcm_msi_alloc(msi, nr_irqs); in brcm_irq_domain_alloc()
554 &brcm_msi_bottom_irq_chip, domain->host_data, in brcm_irq_domain_alloc()
563 struct brcm_msi *msi = irq_data_get_irq_chip_data(d); in brcm_irq_domain_free() local
565 brcm_msi_free(msi, d->hwirq, nr_irqs); in brcm_irq_domain_free()
573 static int brcm_allocate_domains(struct brcm_msi *msi) in brcm_allocate_domains() argument
575 struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np); in brcm_allocate_domains()
576 struct device *dev = msi->dev; in brcm_allocate_domains()
578 msi->inner_domain = irq_domain_add_linear(NULL, msi->nr, &msi_domain_ops, msi); in brcm_allocate_domains()
579 if (!msi->inner_domain) { in brcm_allocate_domains()
581 return -ENOMEM; in brcm_allocate_domains()
584 msi->msi_domain = pci_msi_create_irq_domain(fwnode, in brcm_allocate_domains()
586 msi->inner_domain); in brcm_allocate_domains()
587 if (!msi->msi_domain) { in brcm_allocate_domains()
588 dev_err(dev, "failed to create MSI domain\n"); in brcm_allocate_domains()
589 irq_domain_remove(msi->inner_domain); in brcm_allocate_domains()
590 return -ENOMEM; in brcm_allocate_domains()
596 static void brcm_free_domains(struct brcm_msi *msi) in brcm_free_domains() argument
598 irq_domain_remove(msi->msi_domain); in brcm_free_domains()
599 irq_domain_remove(msi->inner_domain); in brcm_free_domains()
604 struct brcm_msi *msi = pcie->msi; in brcm_msi_remove() local
606 if (!msi) in brcm_msi_remove()
608 irq_set_chained_handler_and_data(msi->irq, NULL, NULL); in brcm_msi_remove()
609 brcm_free_domains(msi); in brcm_msi_remove()
612 static void brcm_msi_set_regs(struct brcm_msi *msi) in brcm_msi_set_regs() argument
614 u32 val = msi->legacy ? BRCM_INT_PCI_MSI_LEGACY_MASK : in brcm_msi_set_regs()
617 writel(val, msi->intr_base + MSI_INT_MASK_CLR); in brcm_msi_set_regs()
618 writel(val, msi->intr_base + MSI_INT_CLR); in brcm_msi_set_regs()
621 * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI in brcm_msi_set_regs()
622 * enable, which we set to 1. in brcm_msi_set_regs()
624 writel(lower_32_bits(msi->target_addr) | 0x1, in brcm_msi_set_regs()
625 msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO); in brcm_msi_set_regs()
626 writel(upper_32_bits(msi->target_addr), in brcm_msi_set_regs()
627 msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI); in brcm_msi_set_regs()
629 val = msi->legacy ? PCIE_MISC_MSI_DATA_CONFIG_VAL_8 : PCIE_MISC_MSI_DATA_CONFIG_VAL_32; in brcm_msi_set_regs()
630 writel(val, msi->base + PCIE_MISC_MSI_DATA_CONFIG); in brcm_msi_set_regs()
635 struct brcm_msi *msi; in brcm_pcie_enable_msi() local
637 struct device *dev = pcie->dev; in brcm_pcie_enable_msi()
639 irq = irq_of_parse_and_map(dev->of_node, 1); in brcm_pcie_enable_msi()
641 dev_err(dev, "cannot map MSI interrupt\n"); in brcm_pcie_enable_msi()
642 return -ENODEV; in brcm_pcie_enable_msi()
645 msi = devm_kzalloc(dev, sizeof(struct brcm_msi), GFP_KERNEL); in brcm_pcie_enable_msi()
646 if (!msi) in brcm_pcie_enable_msi()
647 return -ENOMEM; in brcm_pcie_enable_msi()
649 mutex_init(&msi->lock); in brcm_pcie_enable_msi()
650 msi->dev = dev; in brcm_pcie_enable_msi()
651 msi->base = pcie->base; in brcm_pcie_enable_msi()
652 msi->np = pcie->np; in brcm_pcie_enable_msi()
653 msi->target_addr = pcie->msi_target_addr; in brcm_pcie_enable_msi()
654 msi->irq = irq; in brcm_pcie_enable_msi()
655 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33; in brcm_pcie_enable_msi()
663 if (msi->legacy) { in brcm_pcie_enable_msi()
664 msi->intr_base = msi->base + INTR2_CPU_BASE(pcie); in brcm_pcie_enable_msi()
665 msi->nr = BRCM_INT_PCI_MSI_LEGACY_NR; in brcm_pcie_enable_msi()
666 msi->legacy_shift = 24; in brcm_pcie_enable_msi()
668 msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE; in brcm_pcie_enable_msi()
669 msi->nr = BRCM_INT_PCI_MSI_NR; in brcm_pcie_enable_msi()
670 msi->legacy_shift = 0; in brcm_pcie_enable_msi()
673 ret = brcm_allocate_domains(msi); in brcm_pcie_enable_msi()
677 irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi); in brcm_pcie_enable_msi()
679 brcm_msi_set_regs(msi); in brcm_pcie_enable_msi()
680 pcie->msi = msi; in brcm_pcie_enable_msi()
688 void __iomem *base = pcie->base; in brcm_pcie_rc_mode()
696 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); in brcm_pcie_link_up()
706 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_map_bus()
707 void __iomem *base = pcie->base; in brcm_pcie_map_bus()
714 /* An access to our HW w/o link-up will cause a CPU Abort */ in brcm_pcie_map_bus()
719 idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0); in brcm_pcie_map_bus()
720 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); in brcm_pcie_map_bus()
727 struct brcm_pcie *pcie = bus->sysdata; in brcm7425_pcie_map_bus()
728 void __iomem *base = pcie->base; in brcm7425_pcie_map_bus()
735 /* An access to our HW w/o link-up will cause a CPU Abort */ in brcm7425_pcie_map_bus()
740 idx = PCIE_ECAM_OFFSET(bus->number, devfn, where); in brcm7425_pcie_map_bus()
751 if (pcie->bridge_reset) { in brcm_pcie_bridge_sw_init_set_generic()
753 ret = reset_control_assert(pcie->bridge_reset); in brcm_pcie_bridge_sw_init_set_generic()
755 ret = reset_control_deassert(pcie->bridge_reset); in brcm_pcie_bridge_sw_init_set_generic()
758 dev_err(pcie->dev, "failed to %s 'bridge' reset, err=%d\n", in brcm_pcie_bridge_sw_init_set_generic()
764 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
766 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
776 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
778 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
787 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n")) in brcm_pcie_perst_set_4908()
788 return -EINVAL; in brcm_pcie_perst_set_4908()
791 ret = reset_control_assert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
793 ret = reset_control_deassert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
796 dev_err(pcie->dev, "failed to %s 'perst' reset, err=%d\n", in brcm_pcie_perst_set_4908()
806 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
808 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
817 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
819 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
827 b->size = size; in add_inbound_win()
828 b->cpu_addr = cpu_addr; in add_inbound_win()
829 b->pci_offset = pci_offset; in add_inbound_win()
839 struct device *dev = pcie->dev; in brcm_pcie_get_inbound_wins()
845 * The HW registers (and PCIe) use order-1 numbering for BARs. As such, in brcm_pcie_get_inbound_wins()
846 * we have inbound_wins[0] unused and BAR1 starts at inbound_wins[1]. in brcm_pcie_get_inbound_wins()
848 struct inbound_win *b_begin = &inbound_wins[1]; in brcm_pcie_get_inbound_wins()
858 if (pcie->soc_base != BCM7712) in brcm_pcie_get_inbound_wins()
861 resource_list_for_each_entry(entry, &bridge->dma_ranges) { in brcm_pcie_get_inbound_wins()
862 u64 pcie_start = entry->res->start - entry->offset; in brcm_pcie_get_inbound_wins()
863 u64 cpu_start = entry->res->start; in brcm_pcie_get_inbound_wins()
865 size = resource_size(entry->res); in brcm_pcie_get_inbound_wins()
871 * offering a non-overlapping viewport to system memory. in brcm_pcie_get_inbound_wins()
875 if (pcie->soc_base == BCM7712) in brcm_pcie_get_inbound_wins()
878 if (n > pcie->num_inbound_wins) in brcm_pcie_get_inbound_wins()
883 dev_err(dev, "DT node has no dma-ranges\n"); in brcm_pcie_get_inbound_wins()
884 return -EINVAL; in brcm_pcie_get_inbound_wins()
892 if (pcie->soc_base == BCM7712) in brcm_pcie_get_inbound_wins()
895 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, in brcm_pcie_get_inbound_wins()
899 pcie->num_memc = 1; in brcm_pcie_get_inbound_wins()
900 pcie->memc_size[0] = 1ULL << fls64(tot_size - 1); in brcm_pcie_get_inbound_wins()
902 pcie->num_memc = ret; in brcm_pcie_get_inbound_wins()
906 for (i = 0, size = 0; i < pcie->num_memc; i++) in brcm_pcie_get_inbound_wins()
907 size += pcie->memc_size[i]; in brcm_pcie_get_inbound_wins()
910 size = 1ULL << fls64(size - 1); in brcm_pcie_get_inbound_wins()
921 * whatever the device-tree provides. This is because of an HW issue on in brcm_pcie_get_inbound_wins()
923 * firmware has to dynamically edit dma-ranges due to a bug on the in brcm_pcie_get_inbound_wins()
925 * lower 3GB of memory. Given this, we decided to keep the dma-ranges in brcm_pcie_get_inbound_wins()
926 * in check, avoiding hard to debug device-tree related issues in the in brcm_pcie_get_inbound_wins()
932 * matters, the viewport must start on a pcie-address that is aligned in brcm_pcie_get_inbound_wins()
934 * represent system memory -- e.g. 3GB of memory requires a 4GB in brcm_pcie_get_inbound_wins()
935 * viewport -- we can map the outbound memory in or after 3GB and even in brcm_pcie_get_inbound_wins()
942 * - The best-case scenario, memory up to 3GB, is to place the inbound in brcm_pcie_get_inbound_wins()
943 * region in the first 4GB of pcie-space, as some legacy devices can in brcm_pcie_get_inbound_wins()
944 * only address 32bits. We would also like to put the MSI under 4GB in brcm_pcie_get_inbound_wins()
945 * as well, since some devices require a 32bit MSI target address. in brcm_pcie_get_inbound_wins()
947 * - If the system memory is 4GB or larger we cannot start the inbound in brcm_pcie_get_inbound_wins()
949 * outbound memory @ 3GB). So instead it will start at the 1x in brcm_pcie_get_inbound_wins()
952 if (!size || (pci_offset & (size - 1)) || in brcm_pcie_get_inbound_wins()
956 return -EINVAL; in brcm_pcie_get_inbound_wins()
974 return PCIE_MISC_RC_BAR1_CONFIG_LO + 8 * (bar - 1); in brcm_bar_reg_offset()
976 return PCIE_MISC_RC_BAR4_CONFIG_LO + 8 * (bar - 4); in brcm_bar_reg_offset()
982 return PCIE_MISC_UBUS_BAR1_CONFIG_REMAP + 8 * (bar - 1); in brcm_ubus_reg_offset()
984 return PCIE_MISC_UBUS_BAR4_CONFIG_REMAP + 8 * (bar - 4); in brcm_ubus_reg_offset()
991 void __iomem *base = pcie->base; in set_inbound_win_registers()
994 for (i = 1; i <= num_inbound_wins; i++) { in set_inbound_win_registers()
1015 if (pcie->soc_base == BCM7712) { in set_inbound_win_registers()
1030 void __iomem *base = pcie->base; in brcm_pcie_setup()
1039 ret = pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_setup()
1044 if (pcie->soc_base == BCM2711) { in brcm_pcie_setup()
1045 ret = pcie->perst_set(pcie, 1); in brcm_pcie_setup()
1047 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
1055 ret = pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
1070 * is encoded as 0=128, 1=256, 2=512, 3=Rsvd, for BCM7278 it in brcm_pcie_setup()
1071 * is encoded as 0=Rsvd, 1=128, 2=256, 3=512. in brcm_pcie_setup()
1075 else if (pcie->soc_base == BCM2711) in brcm_pcie_setup()
1077 else if (pcie->soc_base == BCM7278) in brcm_pcie_setup()
1087 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK); in brcm_pcie_setup()
1088 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK); in brcm_pcie_setup()
1090 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK); in brcm_pcie_setup()
1091 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK); in brcm_pcie_setup()
1101 dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n"); in brcm_pcie_setup()
1102 return -EINVAL; in brcm_pcie_setup()
1106 for (memc = 0; memc < pcie->num_memc; memc++) { in brcm_pcie_setup()
1107 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15; in brcm_pcie_setup()
1111 else if (memc == 1) in brcm_pcie_setup()
1112 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(1)); in brcm_pcie_setup()
1119 * We ideally want the MSI target address to be located in the 32bit in brcm_pcie_setup()
1123 * account the rounding-up we're forced to perform). in brcm_pcie_setup()
1127 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; in brcm_pcie_setup()
1129 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; in brcm_pcie_setup()
1132 /* Don't advertise L0s capability if 'aspm-no-l0s' */ in brcm_pcie_setup()
1134 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) in brcm_pcie_setup()
1143 * a PCIe-PCIe bridge (the default setting is to be EP mode). in brcm_pcie_setup()
1151 resource_list_for_each_entry(entry, &bridge->windows) { in brcm_pcie_setup()
1152 struct resource *res = entry->res; in brcm_pcie_setup()
1158 dev_err(pcie->dev, "too many outbound wins\n"); in brcm_pcie_setup()
1159 return -EINVAL; in brcm_pcie_setup()
1163 u64 start = res->start; in brcm_pcie_setup()
1171 start - entry->offset, in brcm_pcie_setup()
1175 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, in brcm_pcie_setup()
1176 res->start - entry->offset, in brcm_pcie_setup()
1181 /* PCIe->SCB endian mode for inbound window */ in brcm_pcie_setup()
1198 const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; in brcm_extend_rbus_timeout()
1202 if (pcie->soc_base == BCM7712) in brcm_extend_rbus_timeout()
1205 /* Each unit in timeout register is 1/216,000,000 seconds */ in brcm_extend_rbus_timeout()
1206 writel(216 * timeout_us, pcie->base + REG_OFFSET); in brcm_extend_rbus_timeout()
1211 static const char err_msg[] = "invalid 'brcm,clkreq-mode' DT string\n"; in brcm_config_clkreq()
1216 ret = of_property_read_string(pcie->np, "brcm,clkreq-mode", &mode); in brcm_config_clkreq()
1217 if (ret && ret != -EINVAL) { in brcm_config_clkreq()
1218 dev_err(pcie->dev, err_msg); in brcm_config_clkreq()
1223 clkreq_cntl = readl(pcie->base + HARD_DEBUG(pcie)); in brcm_config_clkreq()
1226 if (strcmp(mode, "no-l1ss") == 0) { in brcm_config_clkreq()
1228 * "no-l1ss" -- Provides Clock Power Management, L0s, and in brcm_config_clkreq()
1236 * We want to un-advertise L1 substates because if the OS in brcm_config_clkreq()
1239 * "no-l1ss" mode. in brcm_config_clkreq()
1241 tmp = readl(pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP); in brcm_config_clkreq()
1243 writel(tmp, pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP); in brcm_config_clkreq()
1247 * "default" -- Provides L0s, L1, and L1SS, but not in brcm_config_clkreq()
1259 * "safe" -- No power savings; refclk is driven by RC in brcm_config_clkreq()
1263 dev_err(pcie->dev, err_msg); in brcm_config_clkreq()
1266 writel(clkreq_cntl, pcie->base + HARD_DEBUG(pcie)); in brcm_config_clkreq()
1268 dev_info(pcie->dev, "clkreq-mode set to %s\n", mode); in brcm_config_clkreq()
1273 struct device *dev = pcie->dev; in brcm_pcie_start_link()
1274 void __iomem *base = pcie->base; in brcm_pcie_start_link()
1280 if (pcie->gen) in brcm_pcie_start_link()
1281 brcm_pcie_set_gen(pcie, pcie->gen); in brcm_pcie_start_link()
1284 ret = pcie->perst_set(pcie, 0); in brcm_pcie_start_link()
1290 * sections 2.2, PCIe r5.0, 6.6.1. in brcm_pcie_start_link()
1296 * configure RC. Intermittently check status for link-up, up to a in brcm_pcie_start_link()
1304 return -ENODEV; in brcm_pcie_start_link()
1309 if (pcie->ssc) { in brcm_pcie_start_link()
1342 sr->num_supplies = ARRAY_SIZE(supplies); in alloc_subdev_regulators()
1344 sr->supplies[i].supply = supplies[i]; in alloc_subdev_regulators()
1352 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_add_bus()
1353 struct device *dev = &bus->dev; in brcm_pcie_add_bus()
1357 if (!bus->parent || !pci_is_root_bus(bus->parent)) in brcm_pcie_add_bus()
1360 if (dev->of_node) { in brcm_pcie_add_bus()
1367 pcie->sr = sr; in brcm_pcie_add_bus()
1369 ret = regulator_bulk_get(dev, sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1372 pcie->sr = NULL; in brcm_pcie_add_bus()
1376 ret = regulator_bulk_enable(sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1379 regulator_bulk_free(sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1380 pcie->sr = NULL; in brcm_pcie_add_bus()
1391 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_remove_bus()
1392 struct subdev_regulators *sr = pcie->sr; in brcm_pcie_remove_bus()
1393 struct device *dev = &bus->dev; in brcm_pcie_remove_bus()
1395 if (!sr || !bus->parent || !pci_is_root_bus(bus->parent)) in brcm_pcie_remove_bus()
1398 if (regulator_bulk_disable(sr->num_supplies, sr->supplies)) in brcm_pcie_remove_bus()
1400 regulator_bulk_free(sr->num_supplies, sr->supplies); in brcm_pcie_remove_bus()
1401 pcie->sr = NULL; in brcm_pcie_remove_bus()
1404 /* L23 is a low-power PCIe link state */
1407 void __iomem *base = pcie->base; in brcm_pcie_enter_l23()
1413 u32p_replace_bits(&tmp, 1, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK); in brcm_pcie_enter_l23()
1427 dev_err(pcie->dev, "failed to enter low-power link state\n"); in brcm_pcie_enter_l23()
1440 const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1; in brcm_phy_cntl()
1441 const int end = start ? PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS : -1; in brcm_phy_cntl()
1444 void __iomem *base = pcie->base; in brcm_phy_cntl()
1447 for (i = beg; i != end; start ? i++ : i--) { in brcm_phy_cntl()
1459 ret = (tmp & combined_mask) == val ? 0 : -EIO; in brcm_phy_cntl()
1461 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop")); in brcm_phy_cntl()
1468 return pcie->has_phy ? brcm_phy_cntl(pcie, 1) : 0; in brcm_phy_start()
1473 return pcie->has_phy ? brcm_phy_cntl(pcie, 0) : 0; in brcm_phy_stop()
1478 void __iomem *base = pcie->base; in brcm_pcie_turn_off()
1484 ret = pcie->perst_set(pcie, 1); in brcm_pcie_turn_off()
1495 u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); in brcm_pcie_turn_off()
1499 ret = pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_turn_off()
1508 if (device_may_wakeup(&dev->dev)) { in pci_dev_may_wakeup()
1510 dev_info(&dev->dev, "Possible wake-up device; regulators will not be disabled\n"); in pci_dev_may_wakeup()
1533 ret = reset_control_rearm(pcie->rescal); in brcm_pcie_suspend_noirq()
1539 if (pcie->sr) { in brcm_pcie_suspend_noirq()
1542 * downstream device is enabled as a wake-up source, do not in brcm_pcie_suspend_noirq()
1545 pcie->ep_wakeup_capable = false; in brcm_pcie_suspend_noirq()
1546 pci_walk_bus(bridge->bus, pci_dev_may_wakeup, in brcm_pcie_suspend_noirq()
1547 &pcie->ep_wakeup_capable); in brcm_pcie_suspend_noirq()
1548 if (!pcie->ep_wakeup_capable) { in brcm_pcie_suspend_noirq()
1549 ret = regulator_bulk_disable(pcie->sr->num_supplies, in brcm_pcie_suspend_noirq()
1550 pcie->sr->supplies); in brcm_pcie_suspend_noirq()
1553 rret = reset_control_reset(pcie->rescal); in brcm_pcie_suspend_noirq()
1561 clk_disable_unprepare(pcie->clk); in brcm_pcie_suspend_noirq()
1573 base = pcie->base; in brcm_pcie_resume_noirq()
1574 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_resume_noirq()
1578 ret = reset_control_reset(pcie->rescal); in brcm_pcie_resume_noirq()
1587 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_resume_noirq()
1601 if (pcie->sr) { in brcm_pcie_resume_noirq()
1602 if (pcie->ep_wakeup_capable) { in brcm_pcie_resume_noirq()
1609 pcie->ep_wakeup_capable = false; in brcm_pcie_resume_noirq()
1611 ret = regulator_bulk_enable(pcie->sr->num_supplies, in brcm_pcie_resume_noirq()
1612 pcie->sr->supplies); in brcm_pcie_resume_noirq()
1624 if (pcie->msi) in brcm_pcie_resume_noirq()
1625 brcm_msi_set_regs(pcie->msi); in brcm_pcie_resume_noirq()
1630 if (pcie->sr) in brcm_pcie_resume_noirq()
1631 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies); in brcm_pcie_resume_noirq()
1633 rret = reset_control_rearm(pcie->rescal); in brcm_pcie_resume_noirq()
1635 dev_err(pcie->dev, "failed to rearm 'rescal' reset, err=%d\n", rret); in brcm_pcie_resume_noirq()
1637 clk_disable_unprepare(pcie->clk); in brcm_pcie_resume_noirq()
1646 dev_err(pcie->dev, "Could not stop phy\n"); in __brcm_pcie_remove()
1647 if (reset_control_rearm(pcie->rescal)) in __brcm_pcie_remove()
1648 dev_err(pcie->dev, "Could not rearm rescal reset\n"); in __brcm_pcie_remove()
1649 clk_disable_unprepare(pcie->clk); in __brcm_pcie_remove()
1657 pci_stop_root_bus(bridge->bus); in brcm_pcie_remove()
1658 pci_remove_root_bus(bridge->bus); in brcm_pcie_remove()
1759 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1760 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1761 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1762 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7216_cfg },
1763 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1764 { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
1765 { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
1766 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1767 { .compatible = "brcm,bcm7712-pcie", .data = &bcm7712_cfg },
1789 struct device_node *np = pdev->dev.of_node; in brcm_pcie_probe()
1795 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); in brcm_pcie_probe()
1797 return -ENOMEM; in brcm_pcie_probe()
1799 data = of_device_get_match_data(&pdev->dev); in brcm_pcie_probe()
1802 return -EINVAL; in brcm_pcie_probe()
1806 pcie->dev = &pdev->dev; in brcm_pcie_probe()
1807 pcie->np = np; in brcm_pcie_probe()
1808 pcie->reg_offsets = data->offsets; in brcm_pcie_probe()
1809 pcie->soc_base = data->soc_base; in brcm_pcie_probe()
1810 pcie->perst_set = data->perst_set; in brcm_pcie_probe()
1811 pcie->bridge_sw_init_set = data->bridge_sw_init_set; in brcm_pcie_probe()
1812 pcie->has_phy = data->has_phy; in brcm_pcie_probe()
1813 pcie->num_inbound_wins = data->num_inbound_wins; in brcm_pcie_probe()
1815 pcie->base = devm_platform_ioremap_resource(pdev, 0); in brcm_pcie_probe()
1816 if (IS_ERR(pcie->base)) in brcm_pcie_probe()
1817 return PTR_ERR(pcie->base); in brcm_pcie_probe()
1819 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie"); in brcm_pcie_probe()
1820 if (IS_ERR(pcie->clk)) in brcm_pcie_probe()
1821 return PTR_ERR(pcie->clk); in brcm_pcie_probe()
1824 pcie->gen = (ret < 0) ? 0 : ret; in brcm_pcie_probe()
1826 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); in brcm_pcie_probe()
1828 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); in brcm_pcie_probe()
1829 if (IS_ERR(pcie->rescal)) in brcm_pcie_probe()
1830 return PTR_ERR(pcie->rescal); in brcm_pcie_probe()
1832 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst"); in brcm_pcie_probe()
1833 if (IS_ERR(pcie->perst_reset)) in brcm_pcie_probe()
1834 return PTR_ERR(pcie->perst_reset); in brcm_pcie_probe()
1836 pcie->bridge_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "bridge"); in brcm_pcie_probe()
1837 if (IS_ERR(pcie->bridge_reset)) in brcm_pcie_probe()
1838 return PTR_ERR(pcie->bridge_reset); in brcm_pcie_probe()
1840 pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit"); in brcm_pcie_probe()
1841 if (IS_ERR(pcie->swinit_reset)) in brcm_pcie_probe()
1842 return PTR_ERR(pcie->swinit_reset); in brcm_pcie_probe()
1844 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_probe()
1846 return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); in brcm_pcie_probe()
1848 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_probe()
1850 if (pcie->swinit_reset) { in brcm_pcie_probe()
1851 ret = reset_control_assert(pcie->swinit_reset); in brcm_pcie_probe()
1853 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1854 return dev_err_probe(&pdev->dev, ret, in brcm_pcie_probe()
1858 /* HW team recommends 1us for proper sync and propagation of reset */ in brcm_pcie_probe()
1859 udelay(1); in brcm_pcie_probe()
1861 ret = reset_control_deassert(pcie->swinit_reset); in brcm_pcie_probe()
1863 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1864 return dev_err_probe(&pdev->dev, ret, in brcm_pcie_probe()
1865 "could not de-assert reset 'swinit'\n"); in brcm_pcie_probe()
1869 ret = reset_control_reset(pcie->rescal); in brcm_pcie_probe()
1871 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1872 return dev_err_probe(&pdev->dev, ret, "failed to deassert 'rescal'\n"); in brcm_pcie_probe()
1877 reset_control_rearm(pcie->rescal); in brcm_pcie_probe()
1878 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1886 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); in brcm_pcie_probe()
1887 if (pcie->soc_base == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { in brcm_pcie_probe()
1888 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); in brcm_pcie_probe()
1889 ret = -ENODEV; in brcm_pcie_probe()
1894 struct device_node *msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); in brcm_pcie_probe()
1896 if (msi_np == pcie->np) in brcm_pcie_probe()
1902 dev_err(pcie->dev, "probe of internal MSI failed"); in brcm_pcie_probe()
1907 bridge->ops = pcie->soc_base == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops; in brcm_pcie_probe()
1908 bridge->sysdata = pcie; in brcm_pcie_probe()
1914 ret = -ENODEV; in brcm_pcie_probe()
1940 .name = "brcm-pcie",