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/linux-6.14.4/Documentation/devicetree/bindings/display/
Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Kocialkowski <[email protected]>
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
20 synthesis time. As a result, many of the device-tree bindings are meant to
24 Layers are declared in the "layers" sub-node and have dedicated configuration.
25 In version 3 of the controller, each layer has fixed memory offset and address
32 - xylon,logicvc-3.02.a-display
[all …]
/linux-6.14.4/drivers/gpu/drm/atmel-hlcdc/
Datmel_hlcdc_plane.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
10 #include <linux/mfd/atmel-hlcdc.h>
23 * struct atmel_hlcdc_plane_state - Atmel HLCDC Plane state structure.
189 return -ENOTSUPP; in atmel_hlcdc_format_to_plane_mode()
264 factor = (256 * ((8 * (srcsize - 1)) - phidef)) / (dstsize - 1); in atmel_hlcdc_plane_phiscaler_get_factor()
265 max_memsize = ((factor * (dstsize - 1)) + (256 * phidef)) / 2048; in atmel_hlcdc_plane_phiscaler_get_factor()
267 if (max_memsize > srcsize - 1) in atmel_hlcdc_plane_phiscaler_get_factor()
268 factor--; in atmel_hlcdc_plane_phiscaler_get_factor()
281 atmel_hlcdc_layer_write_cfg(&plane->layer, cfg_offs + i, in atmel_hlcdc_plane_scaler_set_phicoeff()
[all …]
/linux-6.14.4/drivers/gpu/drm/xlnx/
Dzynqmp_kms.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP DisplayPort Subsystem - KMS API
5 * Copyright (C) 2017 - 2021 Xilinx, Inc.
8 * - Hyun Woo Kwon <[email protected]>
9 * - Laurent Pinchart <[email protected]>
47 return container_of(drm, struct zynqmp_dpsub_drm, dev)->dpsub; in to_zynqmp_dpsub()
50 /* -----------------------------------------------------------------------------
61 if (!new_plane_state->crtc) in zynqmp_dpsub_plane_atomic_check()
64 crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc); in zynqmp_dpsub_plane_atomic_check()
80 struct zynqmp_dpsub *dpsub = to_zynqmp_dpsub(plane->dev); in zynqmp_dpsub_plane_atomic_disable()
[all …]
/linux-6.14.4/drivers/ata/
Dpata_jmicron.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_jmicron.c - JMicron ATA driver for non AHCI mode. This drives the
31 * jmicron_pre_reset - check for 40/80 pin
38 * either as primary or secondary (or neither). We don't do any policy
44 struct ata_port *ap = link->ap; in jmicron_pre_reset()
45 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in jmicron_pre_reset()
48 int port_mask = 1<< (4 * ap->port_no); in jmicron_pre_reset()
49 int port = ap->port_no; in jmicron_pre_reset()
55 return -ENOENT; in jmicron_pre_reset()
69 as the internal primary channel */ in jmicron_pre_reset()
[all …]
/linux-6.14.4/drivers/gpu/drm/logicvc/
Dlogicvc_layer.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2022 Bootlin
86 struct drm_device *drm_dev = drm_plane->dev; in logicvc_plane_atomic_check()
87 struct logicvc_layer *layer = logicvc_layer(drm_plane); in logicvc_plane_atomic_check() local
96 if (!new_state->crtc) in logicvc_plane_atomic_check()
99 crtc_state = drm_atomic_get_existing_crtc_state(new_state->state, in logicvc_plane_atomic_check()
100 new_state->crtc); in logicvc_plane_atomic_check()
102 return -EINVAL; in logicvc_plane_atomic_check()
104 if (new_state->crtc_x < 0 || new_state->crtc_y < 0) { in logicvc_plane_atomic_check()
106 "Negative on-CRTC positions are not supported.\n"); in logicvc_plane_atomic_check()
[all …]
Dlogicvc_of.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2022 Bootlin
14 { "lvds-4bits", LOGICVC_DISPLAY_INTERFACE_LVDS_4BITS },
15 { "lvds-3bits", LOGICVC_DISPLAY_INTERFACE_LVDS_3BITS },
33 { "layer", LOGICVC_LAYER_ALPHA_LAYER },
40 .name = "xylon,display-interface",
48 .name = "xylon,display-colorspace",
56 .name = "xylon,display-depth",
60 .name = "xylon,row-stride",
67 .name = "xylon,background-layer",
[all …]
Dlogicvc_layer.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2019-2022 Bootlin
32 bool primary; member
53 struct logicvc_layer *layer,
/linux-6.14.4/drivers/gpu/drm/fsl-dcu/
Dfsl_dcu_drm_plane.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private; in fsl_dcu_drm_plane_index()
26 unsigned int total_layer = fsl_dev->soc->total_layer; in fsl_dcu_drm_plane_index()
31 return total_layer - index - 1; in fsl_dcu_drm_plane_index()
33 dev_err(fsl_dev->dev, "No more layer left\n"); in fsl_dcu_drm_plane_index()
34 return -EINVAL; in fsl_dcu_drm_plane_index()
42 struct drm_framebuffer *fb = new_plane_state->fb; in fsl_dcu_drm_plane_atomic_check()
44 if (!new_plane_state->fb || !new_plane_state->crtc) in fsl_dcu_drm_plane_atomic_check()
47 switch (fb->format->format) { in fsl_dcu_drm_plane_atomic_check()
59 return -EINVAL; in fsl_dcu_drm_plane_atomic_check()
[all …]
/linux-6.14.4/drivers/gpu/drm/sun4i/
Dsun4i_layer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
23 if (plane->state) { in sun4i_backend_layer_reset()
24 state = state_to_sun4i_layer_state(plane->state); in sun4i_backend_layer_reset()
26 __drm_atomic_helper_plane_destroy_state(&state->state); in sun4i_backend_layer_reset()
29 plane->state = NULL; in sun4i_backend_layer_reset()
34 __drm_atomic_helper_plane_reset(plane, &state->state); in sun4i_backend_layer_reset()
40 struct sun4i_layer_state *orig = state_to_sun4i_layer_state(plane->state); in sun4i_backend_layer_duplicate_state()
47 __drm_atomic_helper_plane_duplicate_state(plane, &copy->state); in sun4i_backend_layer_duplicate_state()
48 copy->uses_frontend = orig->uses_frontend; in sun4i_backend_layer_duplicate_state()
[all …]
/linux-6.14.4/drivers/gpu/drm/tidss/
Dtidss_crtc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
23 struct drm_device *ddev = tcrtc->crtc.dev; in tidss_crtc_finish_page_flip()
29 spin_lock_irqsave(&ddev->event_lock, flags); in tidss_crtc_finish_page_flip()
37 busy = dispc_vp_go_busy(tidss->dispc, tcrtc->hw_videoport); in tidss_crtc_finish_page_flip()
39 spin_unlock_irqrestore(&ddev->event_lock, flags); in tidss_crtc_finish_page_flip()
43 event = tcrtc->event; in tidss_crtc_finish_page_flip()
44 tcrtc->event = NULL; in tidss_crtc_finish_page_flip()
47 spin_unlock_irqrestore(&ddev->event_lock, flags); in tidss_crtc_finish_page_flip()
51 drm_crtc_send_vblank_event(&tcrtc->crtc, event); in tidss_crtc_finish_page_flip()
[all …]
/linux-6.14.4/drivers/gpu/drm/arm/
Dmalidp_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
29 struct malidp_hw_device *hwdev = malidp->dev; in malidp_crtc_mode_valid()
35 long rate, req_rate = mode->crtc_clock * 1000; in malidp_crtc_mode_valid()
38 rate = clk_round_rate(hwdev->pxlclk, req_rate); in malidp_crtc_mode_valid()
53 struct malidp_hw_device *hwdev = malidp->dev; in malidp_crtc_atomic_enable()
55 int err = pm_runtime_get_sync(crtc->dev->dev); in malidp_crtc_atomic_enable()
62 drm_display_mode_to_videomode(&crtc->state->adjusted_mode, &vm); in malidp_crtc_atomic_enable()
63 clk_prepare_enable(hwdev->pxlclk); in malidp_crtc_atomic_enable()
66 clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000); in malidp_crtc_atomic_enable()
68 hwdev->hw->modeset(hwdev, &vm); in malidp_crtc_atomic_enable()
[all …]
/linux-6.14.4/include/uapi/linux/
Dsctp.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
4 * Copyright (c) 1999-2000 Cisco, Inc.
5 * Copyright (c) 1999-2001 Motorola, Inc.
31 * lksctp developers <linux-[email protected]>
44 * Ryan Layer <[email protected]>
47 * Inaky Perez-Gonzalez <[email protected]>
67 * SCTP <draft-ietf-tsvwg-sctpsocket-07.txt>.
116 /* Options 104-106 are deprecated and removed. Do not use this space */
146 /* PR-SCTP policies */
154 #define __SCTP_PR_INDEX(x) ((x >> 4) - 1)
[all …]
/linux-6.14.4/Documentation/networking/
Dmulti-pf-netdev.rst1 .. SPDX-License-Identifier: GPL-2.0
5 Multi-PF Netdev
11 - `Background`_
12 - `Overview`_
13 - `mlx5 implementation`_
14 - `Channels distribution`_
15 - `Observability`_
16 - `Steering`_
17 - `Mutually exclusive features`_
22 The Multi-PF NIC technology enables several CPUs within a multi-socket server to connect directly to
[all …]
Dip-sysctl.rst1 .. SPDX-License-Identifier: GPL-2.0
10 ip_forward - BOOLEAN
11 - 0 - disabled (default)
12 - not 0 - enabled
20 ip_default_ttl - INTEGER
25 ip_no_pmtu_disc - INTEGER
27 fragmentation-required ICMP is received, the PMTU to this
38 accept fragmentation-needed errors if the underlying protocol
48 Possible values: 0-3
52 min_pmtu - INTEGER
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,ovl-2l.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl-2l.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek display overlay 2 layer
10 - Chun-Kuang Hu <[email protected]>
11 - Philipp Zabel <[email protected]>
14 Mediatek display overlay 2 layer, namely OVL-2L, provides 2 more layer
16 OVL-2L device node must be siblings to the central MMSYS_CONFIG node.
24 - enum:
[all …]
/linux-6.14.4/Documentation/firmware-guide/acpi/apei/
Doutput_format.rst1 .. SPDX-License-Identifier: GPL-2.0
24 [primary][, containment warning][, reset][, threshold exceeded]\
55 [cache error][, TLB error][, bus error][, micro-architectural error]
81 unknown | no error | single-bit ECC | multi-bit ECC | \
82 single-symbol chipkill ECC | multi-symbol chipkill ECC | master abort | \
101 aer_layer=<aer layer string>, aer_agent=<aer agent string>
106 downstream switch port | PCIe to PCI/PCI-X bridge | \
107 PCI/PCI-X to PCIe bridge | root complex integrated endpoint device | \
121 Replay Timer Timeout | Advisory Non-Fatal
124 <aer layer string> :=
[all …]
/linux-6.14.4/drivers/gpu/drm/kmb/
Dkmb_plane.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2018-2020 Intel Corporation
27 /* Conversion (yuv->rgb) matrix from myriadx */
30 1024, -352, -731,
32 -179, 125, -226
35 /* Graphics layer (layers 2 & 3) formats, only packed formats are supported */
48 /* Video layer ( 0 & 1) formats, packed and planar formats are supported */
72 int plane_id = kmb_plane->id; in check_pixel_format()
75 kmb = to_kmb(plane->dev); in check_pixel_format()
76 init_disp_cfg = kmb->init_disp_cfg[plane_id]; in check_pixel_format()
[all …]
/linux-6.14.4/Documentation/core-api/
Dswiotlb.rst1 .. SPDX-License-Identifier: GPL-2.0
7 swiotlb is a memory buffer allocator used by the Linux kernel DMA layer. It is
10 the DMA layer calls swiotlb to allocate a temporary memory buffer that conforms
17 the DMA layer of the DMA attributes of the devices they are managing, and use
19 These APIs use the device DMA attributes and kernel-wide settings to determine
20 if bounce buffering is necessary. If so, the DMA layer manages the allocation,
30 ---------------
33 only provide 32-bit DMA addresses. By allocating bounce buffer memory below
40 directed to guest memory that is unencrypted. CoCo VMs set a kernel-wide option
43 the Linux kernel DMA layer does "sync" operations to cause the CPU to copy the
[all …]
/linux-6.14.4/Documentation/PCI/endpoint/
Dpci-endpoint-cfs.rst1 .. SPDX-License-Identifier: GPL-2.0
17 The PCI Endpoint Core layer creates pci_ep directory in the mounted configfs
20 mount -t configfs none /sys/kernel/config
73 ... primary/
79 Non-transparent bridge), symlink of endpoint controller connected to primary
80 interface should be added in 'primary' directory and symlink of endpoint
138 [1] Documentation/PCI/endpoint/pci-endpoint.rst
/linux-6.14.4/drivers/gpu/drm/arm/display/komeda/
Dkomeda_plane.c1 // SPDX-License-Identifier: GPL-2.0
20 struct komeda_plane *kplane = to_kplane(st->plane); in komeda_plane_init_data_flow()
21 struct drm_framebuffer *fb = st->fb; in komeda_plane_init_data_flow()
22 const struct komeda_format_caps *caps = to_kfb(fb)->format_caps; in komeda_plane_init_data_flow()
23 struct komeda_pipeline *pipe = kplane->layer->base.pipeline; in komeda_plane_init_data_flow()
27 dflow->blending_zorder = st->normalized_zpos; in komeda_plane_init_data_flow()
28 if (pipe == to_kcrtc(st->crtc)->master) in komeda_plane_init_data_flow()
29 dflow->blending_zorder -= kcrtc_st->max_slave_zorder; in komeda_plane_init_data_flow()
30 if (dflow->blending_zorder < 0) { in komeda_plane_init_data_flow()
32 st->plane->name, st->normalized_zpos, in komeda_plane_init_data_flow()
[all …]
/linux-6.14.4/drivers/s390/net/
Dqeth_core_mpc.c1 // SPDX-License-Identifier: GPL-2.0
145 {IPA_RC_IP_TABLE_FULL, "Add Addr IP Table Full - ipv6"},
146 {IPA_RC_UNKNOWN_ERROR, "IPA command failed - reason unknown"},
156 {IPA_RC_SBP_IQD_ANO_DEV_PRIMARY, "Primary bridgeport exists already"},
160 {IPA_RC_SBP_IQD_CURRENT_PRIMARY, "Bridgeport is currently primary"},
163 {IPA_RC_L2_UNSUPPORTED_CMD, "Unsupported layer 2 command"},
166 {IPA_RC_L2_DUP_LAYER3_MAC, "Duplicate with layer 3 MAC"},
177 {IPA_RC_SBP_OSA_ANO_DEV_PRIMARY, "Primary bridgeport exists already"},
181 {IPA_RC_SBP_OSA_CURRENT_PRIMARY, "Bridgeport is currently primary"},
197 {IPA_RC_PRIMARY_ALREADY_DEFINED, "Primary already defined"},
[all …]
/linux-6.14.4/drivers/gpu/drm/stm/
Dltdc.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/media-bus-format.h>
46 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
61 #define LAY_OFS (ldev->caps.layer_ofs)
65 #define LTDC_LCR 0x0004 /* Layer Count */
86 /* Layer register offsets */
87 #define LTDC_L1C0R (ldev->caps.layer_regs[0]) /* L1 configuration 0 */
88 #define LTDC_L1C1R (ldev->caps.layer_regs[1]) /* L1 configuration 1 */
89 #define LTDC_L1RCR (ldev->caps.layer_regs[2]) /* L1 reload control */
90 #define LTDC_L1CR (ldev->caps.layer_regs[3]) /* L1 control register */
[all …]
/linux-6.14.4/Documentation/arch/s390/
Dcds.rst9 - Ingo Adlung
10 - Cornelia Huck
12 Copyright, IBM Corp. 1999-2002
21 processing, shared versus non-shared interrupt processing, DMA versus port
30 Operation manual (IBM Form. No. SA22-7201).
33 functional layer was introduced that provides generic I/O access methods to
36 The common device support layer comprises the I/O support routines defined
42 described in Documentation/arch/s390/driver-model.rst.
49 * All drivers must define a ccw_driver (see driver-model.txt) and the associated
56 * The channel device layer is gone.
[all …]
/linux-6.14.4/include/net/sctp/
Dcommand.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1999-2001 Cisco, Motorola
12 * lksctp developers <linux-[email protected]>
39 SCTP_CMD_CHUNK_ULP, /* Send a chunk to the sockets layer. */
40 SCTP_CMD_EVENT_ULP, /* Send a notification to the sockets layer. */
55 SCTP_CMD_COOKIEECHO_RESTART, /* High level, do cookie-echo timer work. */
73 SCTP_CMD_SETUP_T2, /* Hi-level, setup T2-shutdown parms. */
82 SCTP_CMD_DEL_NON_PRIMARY, /* Removes non-primary peer transports. */
83 SCTP_CMD_T3_RTX_TIMERS_STOP, /* Stops T3-rtx pending timers */
84 SCTP_CMD_FORCE_PRIM_RETRAN, /* Forces retrans. over primary path. */
[all …]
/linux-6.14.4/drivers/parisc/
Dpdc_stable.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Thibaut VARENE <varenet@parisc-linux.org>
14 * all) PA-RISC machines should have them. Anyway, for safety reasons, the
18 * One last word: there's one path we can always count on: the primary path.
19 * Anything above 224 bytes is used for 'osdep2' OS-dependent storage area.
21 * The first OS-dependent area should always be available. Obviously, this is
24 * NOTE: We do not handle the 2 bytes OS-dep area at 0x5D, nor the first
26 * sacrificed: -ETOOLAZY :P
29 * - write: root only
30 * - read: (reading triggers PDC calls) ? root only : everyone
[all …]

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