| /aosp_15_r20/external/mesa3d/src/intel/ci/ |
| H A D | gitlab-ci.yml | 2 - local: 'src/intel/ci/gitlab-ci-inc.yml'
4 anv-jsl:
6 - .lava-acer-cb317-1h-c3z6-dedede:x86_64
7 - .anv-test
9 DEQP_SUITE: anv-jsl
10 VK_DRIVER: intel
14 # We don't enable a full run of anv-jsl nightly because it's about 8 hours of
16 .anv-jsl-full:
18 - anv-jsl
19 - .anv-manual-rules
[all …]
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| H A D | gitlab-ci-inc.yml | 1 .intel-common-rules:
2 stage: intel
4 - changes: &intel_common_file_list
5 - src/intel/*
6 - src/intel/blorp/**/*
7 - src/intel/common/**/*
8 - src/intel/compiler/**/*
9 - src/intel/dev/**/*
10 - src/intel/ds/**/*
11 - src/intel/genxml/**/*
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| /aosp_15_r20/external/coreboot/src/soc/intel/alderlake/ |
| H A D | Kconfig | 1 ## SPDX-License-Identifier: GPL-2.0-only
101 Intel Alderlake support. Mainboards should specify the PCH
109 Intel Raptorlake support. Mainboards using RPL should select
116 Intel Twinlake support. Mainboards using TWL should select
124 Choose this option if your mainboard has a PCH-N chipset.
132 Choose this option if your mainboard has a PCH-P chipset.
140 Choose this option if your mainboard has a PCH-S chipset.
147 Choose this option if your mainboard has a Raptor Lake PCH-S chipset.
189 The size of the cache-as-ram region required during bootblock
198 sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement
[all …]
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| H A D | fsp_params.c | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 #include <cpu/intel/microcode.h>
13 #include <drivers/intel/gma/i915_reg.h>
30 #include <soc/intel/common/vbt.h>
59 * 0 - Disable EOP.
60 * 1 - Send in PEI (Applicable for FSP in API mode)
61 * 2 - Send in DXE (Not applicable for FSP in API mode)
439 if (is_pch_slot(entry->devfn)) in pci_irq_to_fsp()
441 entry = entry->next; in pci_irq_to_fsp()
448 if (!is_pch_slot(entry->devfn)) { in pci_irq_to_fsp()
[all …]
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| /aosp_15_r20/external/skia/src/gpu/ganesh/gl/ |
| H A D | GrGLUtil.cpp | 4 * Use of this source code is governed by a BSD-style license that can be
60 n = sscanf(versionString, "OpenGL ES-%c%c %d.%d", profile, profile+1, &major, &minor); in GrGLGetStandardInUseFromString()
102 n = sscanf(versionString, "OpenGL ES-%c%c %d.%d", profile, profile + 1, &major, &minor); in GrGLGetVersionFromString()
158 if (0 == strncmp(vendorString, "Intel ", 6) || 0 == strcmp(vendorString, "Intel")) { in get_vendor()
179 if (0 == strncmp(rendererString, kTegraStr, std::size(kTegraStr) - 1)) { in get_renderer()
190 if (strstr(rendererString, "PowerVR B-Series")) { in get_renderer()
197 if (0 == strncmp(rendererString, kAppleA4Str, std::size(kAppleA4Str) - 1) || in get_renderer()
198 0 == strncmp(rendererString, kAppleA5Str, std::size(kAppleA5Str) - 1) || in get_renderer()
199 0 == strncmp(rendererString, kAppleA6Str, std::size(kAppleA6Str) - 1)) { in get_renderer()
205 if (0 == strncmp(rendererString, kPowerVRRogueStr, std::size(kPowerVRRogueStr) - 1) || in get_renderer()
[all …]
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| /aosp_15_r20/external/coreboot/src/mainboard/intel/adlrvp/ |
| H A D | Kconfig | 1 ## SPDX-License-Identifier: GPL-2.0-only
89 But since ADL RVP build can be used with or without CSE Lite firmware
103 default "intel/adlrvp"
117 default "ADLRVPN TEST 7673" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC
118 default "ADLRVPP TEST 2418"
125 default "Intel Corporation"
143 Select whether the board has Intel EC or Chrome EC
154 bool "Intel EC"
183 Support external Gen-3 clock chip for ADL-P.
|
| /aosp_15_r20/external/mesa3d/src/gallium/drivers/zink/ci/ |
| H A D | gitlab-ci-inc.yml | 1 .zink-common-rules:
3 - !reference [.test, rules]
4 - !reference [.gl-rules, rules]
5 - changes: &zink_files_list
6 - src/gallium/drivers/zink/*
7 - src/gallium/drivers/zink/nir_to_spirv/*
8 - src/gallium/drivers/zink/ci/gitlab-ci.yml
9 - src/gallium/drivers/zink/ci/gitlab-ci-inc.yml
10 - src/gallium/drivers/zink/ci/deqp-$DEQP_SUITE.toml
11 - src/gallium/drivers/zink/ci/$GPU_VERSION-fails.txt
[all …]
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| /aosp_15_r20/external/mesa3d/docs/relnotes/ |
| H A D | 21.2.3.rst | 1 Mesa 21.2.3 Release Notes / 2021-09-29
18 ---------------
22 7245284a159d2484770e1835a673e79e4322a9ddf43b17859668244946db7174 mesa-21.2.3.tar.xz
26 ------------
28 - None
32 ---------
34 - Significant performance drop on Radeon HD 8400
35 - [nir][radv] Out of range shift when compiling Resident Evil Village shaders
36 - [nir][radv] Out of range shift when compiling Resident Evil Village shaders
37 - GL_EXT_disjoint_timer_query glGetInteger64v GL_TIMESTAMP failing with GL_INVALID_ENUM
[all …]
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| H A D | 21.3.0.rst | 1 Mesa 21.3.0 Release Notes / 2021-11-17
20 ---------------
24 a2753c09deef0ba14d35ae8a2ceff3fe5cd13698928c7bb62c2ec8736eb09ce1 mesa-21.3.0.tar.xz
28 ------------
30 - VK_EXT_color_write_enable on lavapipe
31 - GL_ARB_texture_filter_anisotropic in llvmpipe
32 - Anisotropic texture filtering in lavapipe
33 - VK_EXT_shader_atomic_float2 on Intel and RADV.
34 - VK_EXT_vertex_input_dynamic_state on RADV.
35 - VK_KHR_timeline_semaphore on lavapipe
[all …]
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| H A D | 23.1.4.rst | 1 Mesa 23.1.4 Release Notes / 2023-07-21
18 ---------------
22 7261a17fb94867e3dc5a90d8a1f100fa04b0cbbde51d25302c0872b5e9a10959 mesa-23.1.4.tar.xz
26 ------------
28 - None
32 ---------
34 - radeonsi: Deadlock when creating a new GL context in parallel with linking a shader on another GL…
35 - robustness2 raygen tests intermittently fail in Intel Mesa CI
36 - glthread: huge performance regression
37 - DirectX games do not launch on Intel HD Graphics 4000 (IVB GT2) [bisected]
[all …]
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| H A D | 21.1.2.rst | 1 Mesa 21.1.2 Release Notes / 2021-06-02
18 ---------------
22 23b4b63760561f3a4f98b5be12c6de621e9a6bdf355e087a83d9184cd4e2825f mesa-21.1.2.tar.xz
26 ------------
28 - None
32 ---------
34 - zink: regression for primitive-restart on ANV
35 - zink: Expected Image Operand ConstOffset to be a const object
36 - [RADV] - Path of Exile (238960) - Ground decals are missing or corrupted using the Vulkan rendere…
37 - [ADL-S / TGL-U / TGL-H] Pixels missing / flickering when render some app on weston
[all …]
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| H A D | 21.2.0.rst | 1 Mesa 21.2.0 Release Notes / 2021-08-04
20 ---------------
24 0cb3c802f4b8e7699b1602c08c29d06a4d532ab5b8f7a64676c4ca6bb8f4d426 mesa-21.2.0.tar.xz
28 ------------
30 - zink supports GL_ARB_texture_filter_minmax, GL_ARB_shader_clock
32 - VK_EXT_provoking_vertex on RADV.
34 - VK_EXT_extended_dynamic_state2 on RADV.
36 - VK_EXT_global_priority_query on RADV.
38 - VK_EXT_physical_device_drm on RADV.
40 - VK_KHR_shader_subgroup_uniform_control_flow on Intel and RADV.
[all …]
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| H A D | 22.3.0.rst | 1 Mesa 22.3.0 Release Notes / 2022-12-02
20 ---------------
24 644bf936584548c2b88762111ad58b4aa3e4688874200e5a4eb74e53ce301746 mesa-22.3.0.tar.xz
28 ------------
30 - GL_ARB_shader_clock on llvmpipe
31 - VK_KHR_shader_clock on lavapipe
32 - Mesa-DB, the new single file cache type
33 - VK_EXT_attachment_feedback_loop_layout on RADV, lavapipe
34 - VK_KHR_global_priority on RADV
35 - GL_KHR_blend_equation_advanced_coherent on zink
[all …]
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| H A D | 22.2.0.rst | 1 Mesa 22.2.0 Release Notes / 2022-09-21
20 ---------------
24 b1f9c8fd08f2cae3adf83355bef4d2398e8025f44947332880f2d0066bdafa8c mesa-22.2.0.tar.xz
29 ------------
31 - WGL_ARB_create_context_robustness
33 - d3d12 ARB_robust_buffer_access_behavior
35 - VK_EXT_robustness2 for lavapipe
37 - VK_EXT_image_2d_view_of_3d on RADV
39 - zink and d3d12 GL_EXT_memory_object_win32 and GL_EXT_semaphore_win32 support
41 - vertexAttributeInstanceRateZeroDivisor support for lavapipe
[all …]
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| H A D | 22.0.0.rst | 1 Mesa 22.0.0 Release Notes / 2022-03-09
20 ---------------
24 e6c41928b5b9917485bd67cec22d15e62cad7a358bf4c711a647979987601250 mesa-22.0.0.tar.xz
28 ------------
30 - lavapipe,radv,anv KHR_dynamic_rendering
31 - radv EXT_image_view_min_lod
32 - VK_KHR_synchronization2 on RADV.
33 - OpenSWR has been moved to the Amber branch
34 - radeonsi, zink ARB_sparse_texture
35 - d3d12 GLES3.1 (shader storage buffers, images, compute, indirect draw, draw params, ARB_framebuff…
[all …]
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| H A D | 24.1.0.rst | 1 Mesa 24.1.0 Release Notes / 2024-05-22
20 ---------------
24 b7eac8c79244806b1c276eeeacc329e4a5b31a370804c4b0c7cd16837783f78b mesa-24.1.0.tar.xz
28 ------------
30 - VK_EXT_map_memory_placed on RADV, ANV and NVK
31 - VK_KHR_shader_subgroup_rotate on RADV and ANV and NVK
32 - VK_KHR_load_store_op_none on RADV, ANV, NVK and Turnip
33 - VK_KHR_line_rasterization on RADV, ANV, NVK and Turnip
34 - VK_KHR_index_type_uint8 on RADV, ANV, NVK and Turnip
35 - VK_KHR_shader_expect_assume on all Vulkan drivers
[all …]
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| /aosp_15_r20/external/mesa3d/src/intel/dev/ |
| H A D | meson.build | 1 # Copyright © 2017 Intel Corporation
2 # SPDX-License-Identifier: MIT
60 test('intel_device_info_test',
67 suite : ['intel'],
71 if with_tests and with_tools.contains('drm-shim') and with_tools.contains('intel')
77 [ 120, ['tgl', 'rkl', 'adl', 'rpl', 'dg1', 'sg1'] ],
90 test('intel_device_info_override_test_@0@'.format(p),
96 'STRACEDIR=meson-logs/strace/intel_device_info_override_test_@0@'.format(p),
98 suite : ['intel'],
|
| /aosp_15_r20/external/sdv/vsomeip/third_party/boost/optional/test/ |
| D | optional_test.cpp | 21 #include "boost/bind/apply.hpp" // Included just to test proper interaction with boost::apply<> as …
58 // Basic test.
60 // Initialization, assignment, comparison and value-accessing.
94 // Value-Assignment upon Uninitialized optional. in test_basics()
102 // Value-Assignment upon Initialized optional. in test_basics()
176 …optional<T> def1 = boost::make_optional(false,a); // T is not within boost so ADL won't find make… in test_conditional_ctor_and_get_valur_or()
183 …optional<T> o1 = boost::make_optional(true,a); // T is not within boost so ADL won't find make_op… in test_conditional_ctor_and_get_valur_or()
253 // Test Direct Value Manipulation
268 BOOST_TEST( c_opt0->V() == x.V() ) ; in test_direct_value_manip()
269 BOOST_TEST( opt0->V() == x.V() ) ; in test_direct_value_manip()
[all …]
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| /aosp_15_r20/external/coreboot/Documentation/ |
| H A D | acronyms.md | 4 ## _0-9
6 * _XXX - An underscore followed by 3 uppercase letters will typically be
10 * 2FA - [**Two-factor Authentication**](https://en.wikipedia.org/wiki/Multi-factor_authentication)
11 * 4G - In coreboot, this typically refers to the 4 gibibyte boundary of 32-bit addressable memory s…
13 * 5G - Telecommunication: [**Fifth-Generation Cellular Network**](https://en.wikipedia.org/wiki/5G)
16 * ABI - [**Application Binary Interface**](https://en.wikipedia.org/wiki/Application_binary_interfa…
17 * ABL - AMD: AGESA BootLoader (or AMD BootLoader) - The portion of the AMD processor
20 * AC - Electricity: [**Alternating Current**](https://en.wikipedia.org/wiki/Alternating_current)
21 * Ack - Acknowledgment / Acknowledged
22 * ACM – [**Authenticated Code Module**](https://doc.coreboot.org/security/intel/acm.html)
[all …]
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| /aosp_15_r20/out/.module_paths/ |
| D | configuration.list | 7 art/test/Android.run-test.mk
46 build/make/core/combo/TARGET_linux-arm.mk
47 build/make/core/combo/TARGET_linux-arm64.mk
48 build/make/core/combo/TARGET_linux-riscv64.mk
49 build/make/core/combo/TARGET_linux-x86.mk
50 build/make/core/combo/TARGET_linux-x86_64.mk
51 build/make/core/combo/arch/arm/armv7-a-neon.mk
52 build/make/core/combo/arch/arm/armv8-2a.mk
53 build/make/core/combo/arch/arm/armv8-a.mk
54 build/make/core/combo/arch/arm64/armv8-2a-dotprod.mk
[all …]
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/ |
| H A D | FspsUpd.h | 3 Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
13 * Neither the name of Intel Corporation nor the names of its contributors may
77 UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
88 /** Offset 0x0040 - Logo Pointer
93 /** Offset 0x0044 - Logo Size
98 /** Offset 0x0048 - Blt Buffer Address
103 /** Offset 0x004C - Blt Buffer Size
109 /** Offset 0x0050 - Graphics Configuration Ptr
114 /** Offset 0x0054 - Enable Device 4
120 /** Offset 0x0055 - Show SPI controller
[all …]
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/twinlake/ |
| H A D | FspsUpd.h | 3 Copyright (c) 2022 - 2024, Intel Corporation. All rights reserved.<BR>
13 * Neither the name of Intel Corporation nor the names of its contributors may
77 UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
88 /** Offset 0x0040 - Logo Pointer
93 /** Offset 0x0044 - Logo Size
98 /** Offset 0x0048 - Blt Buffer Address
103 /** Offset 0x004C - Blt Buffer Size
109 /** Offset 0x0050 - Graphics Configuration Ptr
114 /** Offset 0x0054 - Enable Device 4
120 /** Offset 0x0055 - Show SPI controller
[all …]
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/alderlake/ |
| H A D | FspsUpd.h | 3 Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
13 * Neither the name of Intel Corporation nor the names of its contributors may
77 UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
88 /** Offset 0x0040 - Logo Pointer
93 /** Offset 0x0044 - Logo Size
98 /** Offset 0x0048 - Blt Buffer Address
103 /** Offset 0x004C - Blt Buffer Size
109 /** Offset 0x0050 - Graphics Configuration Ptr
114 /** Offset 0x0054 - Enable Device 4
120 /** Offset 0x0055 - Show SPI controller
[all …]
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/raptorlake/ |
| H A D | FspsUpd.h | 3 Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
13 * Neither the name of Intel Corporation nor the names of its contributors may
77 UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
88 /** Offset 0x0040 - Logo Pointer
93 /** Offset 0x0044 - Logo Size
98 /** Offset 0x0048 - Blt Buffer Address
103 /** Offset 0x004C - Blt Buffer Size
109 /** Offset 0x0050 - Graphics Configuration Ptr
114 /** Offset 0x0054 - Enable Device 4
120 /** Offset 0x0055 - Show SPI controller
[all …]
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| H A D | FspmUpd.h | 3 Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
13 * Neither the name of Intel Corporation nor the names of its contributors may
58 /** Offset 0x0040 - Platform Reserved Memory Size
63 /** Offset 0x0048 - SPD Data Length
69 /** Offset 0x004A - Enable above 4GB MMIO resource support
75 /** Offset 0x004B - Enable/Disable CrashLog Device 10
81 /** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0
86 /** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1
91 /** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0
96 /** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1
[all …]
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