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/linux-6.14.4/Documentation/devicetree/bindings/pci/
Dsnps,dw-pcie-ep.yaml33 normal controller functioning. iATU memory IO region is also required
47 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
68 iATU/eDMA registers common for all device functions. It's an
73 set of viewport CSRs mapped into the PL space. Note iATU is
92 Outbound iATU-capable memory-region which will be used to
Dsnps,dw-pcie.yaml42 are required for the normal controller work. iATU memory IO region is
56 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
77 iATU/eDMA registers common for all device functions. It's an
82 set of viewport CSRs mapped into the PL space. Note iATU is
101 Outbound iATU-capable memory-region which will be used to access
Dsnps,dw-pcie-common.yaml27 iATU/eDMA registers. The particular sub-space is selected by the
232 auto-detected based on the iATU memory writability. So there is no
242 on the iATU memory writability. There is no point having a dedicated
259 configuration space registers, Port Logic registers, DMA and iATU
Dbaikal,bt1-pcie.yaml18 performed by software. There four in- and four outbound iATU regions
30 DBI, DBI2 and at least 4KB outbound iATU-capable region for the
Dnvidia,tegra194-pcie-ep.yaml35 - description: iATU and DMA registers. This is where the iATU (internal
Drockchip-dw-pcie-ep.yaml33 - description: Internal Address Translation Unit (iATU) registers
Dnvidia,tegra194-pcie.yaml34 - description: iATU and DMA registers. This is where the iATU (internal
/linux-6.14.4/drivers/pci/controller/dwc/
Dpcie-designware.h67 /* Parameters for the waiting for iATU enabled routine */
149 * iATU inbound and outbound windows CSRs. Before the IP-core v4.80a each
150 * iATU region CSRs had been indirectly accessible by means of the dedicated
151 * viewport selector. The iATU/eDMA CSRs space was re-designed in DWC PCIe
153 * iATU/eDMA CSRs space.
195 * introduced so eDMA and iATU could be accessed via a dedicated registers
232 * iATU Unroll-specific register definitions
Dpcie-designware.c130 /* For non-unrolled iATU/eDMA platforms this range will be ignored */ in dw_pcie_get_resources()
531 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); in dw_pcie_prog_outbound_atu()
594 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in dw_pcie_prog_inbound_atu()
631 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in dw_pcie_prog_ep_inbound_atu()
825 dev_err(pci->dev, "No iATU regions found\n"); in dw_pcie_iatu_detect()
844 dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n", in dw_pcie_iatu_detect()
Dpcie-designware-host.c508 * Allocate the resource for MSG TLP before programming the iATU in dw_pcie_host_init()
715 dev_err(pci->dev, "No outbound iATU found\n"); in dw_pcie_iatu_setup()
742 /* Adjust iATU size if MSG TLP region was allocated before */ in dw_pcie_iatu_setup()
777 dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n", in dw_pcie_iatu_setup()
802 dev_warn(pci->dev, "Dma-ranges exceed inbound iATU size (%u)\n", in dw_pcie_iatu_setup()
Dpcie-dw-rockchip.c286 * iATU settings for BAR4. This means that BAR4 cannot be used by an EPF driver,
288 * default.) If the host could write to BAR4, the iATU settings (for all other
Dpci-imx6.c1237 * In old DWC implementations, PCIE_ATU_INHIBIT_PAYLOAD in iATU Ctrl2
/linux-6.14.4/drivers/accel/habanalabs/common/pci/
Dpci.c206 * hl_pci_iatu_write() - iatu write routine.
241 * Configure the iATU inbound region.
304 * Configure the iATU outbound region 0.
404 /* Driver must sleep in order for FW to finish the iATU configuration */ in hl_pci_init()
/linux-6.14.4/include/linux/dma/
Dedma.h40 * iATU windows. That will be done by the controller
/linux-6.14.4/include/linux/habanalabs/
Dhl_boot_if.h283 * CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN FW iATU configuration is enabled.
284 * This bit if set, means the iATU has been
/linux-6.14.4/drivers/accel/habanalabs/goya/
Dgoya.c551 * goya_init_iatu - Initialize the iATU unit inside the PCI controller
555 * This is needed in case the firmware doesn't initialize the iATU
655 /* Check whether FW is configuring iATU */ in goya_early_init()
2744 * iATU to point to the start address of the MMU page tables in goya_hw_init()
/linux-6.14.4/drivers/accel/habanalabs/common/
Dhabanalabs.h685 * @iatu_done_by_fw: true if iATU configuration is being done by FW.
1586 * @init_iatu: Initialize the iATU unit inside the PCI controller.
/linux-6.14.4/drivers/accel/habanalabs/gaudi/
Dgaudi.c855 /* Check whether FW is configuring iATU */ in gaudi_early_init()
3922 /* If iATU is done by FW, the HBM bar ALWAYS points to DRAM_PHYS_BASE. in gaudi_hw_init()
/linux-6.14.4/drivers/accel/habanalabs/gaudi2/
Dgaudi2.c3136 * Only in pldm driver config iATU in gaudi2_early_init()
6142 /* If iATU is done by FW, the HBM bar ALWAYS points to DRAM_PHYS_BASE. in gaudi2_hw_init()