Home
last modified time | relevance | path

Searched +full:half +full:- +full:period (Results 1 – 25 of 323) sorted by relevance

12345678910>>...13

/linux-6.14.4/Documentation/input/devices/
Drotary-encoder.rst2 rotary-encoder - a generic driver for GPIO connected devices
8 --------
11 peripherals with two wires. The outputs are phase-shifted by 90 degrees
16 a stable state with both outputs high (half-period mode) and some have
17 a stable state in all steps (quarter-period mode).
33 |<-------->|
36 |<-->|
37 one step (half-period mode)
40 one step (quarter-period mode)
47 ----------------------
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/input/
Drotary-encoder.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/rotary-encoder.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <[email protected]>
13 See Documentation/input/devices/rotary-encoder.rst for more information.
17 const: rotary-encoder
28 rotary-encoder,steps:
36 rotary-encoder,relative-axis:
40 absolute one. Relative axis will only generate +1/-1 events on the input
[all …]
/linux-6.14.4/sound/soc/fsl/
Dlpc3xxx-i2s.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 struct mutex lock; /* To serialize user-space access */
50 #define LPC3XXX_I2S_WS_HP(s) FIELD_PREP(0x7FC0, s) /* Word select half period - 1 */
53 #define LPC3XXX_I2S_WW32_HP 0x1f /* Word select half period for 32bit word width */
54 #define LPC3XXX_I2S_WW16_HP 0x0f /* Word select half period for 16bit word width */
55 #define LPC3XXX_I2S_WW8_HP 0x7 /* Word select half period for 8bit word width */
/linux-6.14.4/drivers/video/fbdev/
Dcontrolfb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
49 struct preg vperiod; /* vert period */
52 struct preg hperiod; /* horiz period - 2 */
57 struct preg heq; /* half horiz sync len */
58 struct preg hlfln; /* half horiz period */
59 struct preg hserr; /* horiz period - horiz sync len */
81 unsigned vperiod; /* vert period */
85 unsigned hperiod; /* horiz period - 2 */
90 unsigned heq; /* half horiz sync len */
91 unsigned hlfln; /* half horiz period */
[all …]
/linux-6.14.4/include/linux/
Dcnt32_to_63.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Extend a 32-bit counter to 63 bits
31 * cnt32_to_63 - Expand a 32-bit counter to a 63-bit counter
35 * a relatively short period making wrap-arounds rather frequent. This
36 * is a problem when implementing sched_clock() for example, where a 64-bit
37 * non-wrapping monotonic value is expected to be returned.
39 * To overcome that limitation, let's extend a 32-bit counter to 63 bits
42 * memory is used to synchronize with the hardware clock half-period. When
55 * 1) this code must be called at least once per each half period of the
56 * 32-bit counter;
[all …]
/linux-6.14.4/drivers/input/misc/
Drotary_encoder.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * See file:Documentation/input/devices/rotary-encoder.rst for more information
26 #define DRV_NAME "rotary-encoder"
51 signed char dir; /* 1 - clockwise, -1 - CCW */
61 for (i = 0; i < encoder->gpios->ndescs; ++i) { in rotary_encoder_get_state()
62 int val = gpiod_get_value_cansleep(encoder->gpios->desc[i]); in rotary_encoder_get_state()
65 if (encoder->encoding == ROTENC_GRAY && ret & 1) in rotary_encoder_get_state()
76 if (encoder->relative_axis) { in rotary_encoder_report_event()
77 input_report_rel(encoder->input, in rotary_encoder_report_event()
78 encoder->axis, encoder->dir); in rotary_encoder_report_event()
[all …]
/linux-6.14.4/drivers/net/ethernet/cavium/liquidio/
Docteon_config.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
25 /*--------------------------CONFIG VALUES------------------------*/
121 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
122 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs)
123 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size)
124 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
125 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
126 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout)
128 #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt)
[all …]
/linux-6.14.4/tools/perf/Documentation/
Dtopdown.txt2 ---------------------
11 perf stat --topdown implements this using available metrics that vary
14 % perf stat -a --topdown -I1000
84 int slots_fd = perf_event_open(&slots, 0, -1, -1, 0);
104 int metrics_fd = perf_event_open(&metrics, 0, -1, slots_fd, 0);
188 for that time period.
205 retiring_slots = GET_METRIC(metric_b, 0) * slots_b - retiring_slots_a
206 bad_spec_slots = GET_METRIC(metric_b, 1) * slots_b - bad_spec_slots_a
207 fe_bound_slots = GET_METRIC(metric_b, 2) * slots_b - fe_bound_slots_a
208 be_bound_slots = GET_METRIC(metric_b, 3) * slots_b - be_bound_slots_a
[all …]
/linux-6.14.4/sound/soc/meson/
Daxg-fifo.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
15 #include <sound/soc-dai.h>
17 #include "axg-fifo.h"
65 return dai->dev; in axg_fifo_dev()
70 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_DMA_EN, in __dma_enable()
91 return -EINVAL; in axg_fifo_pcm_trigger()
102 struct snd_pcm_runtime *runtime = ss->runtime; in axg_fifo_pcm_pointer()
105 regmap_read(fifo->map, FIFO_STATUS2, &addr); in axg_fifo_pcm_pointer()
107 return bytes_to_frames(runtime, addr - (unsigned int)runtime->dma_addr); in axg_fifo_pcm_pointer()
115 struct snd_pcm_runtime *runtime = ss->runtime; in axg_fifo_pcm_hw_params()
[all …]
/linux-6.14.4/Documentation/arch/arm/stm32/
Dstm32-dma-mdma-chaining.rst1 .. SPDX-License-Identifier: GPL-2.0
4 STM32 DMA-MDMA chaining
9 ------------
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
44 ----------
46 STM32 DMA-MDMA chaining feature relies on the strengths of STM32 DMA and
50 (when DMA data counter - DMA_SxNDTR - reaches 0), the memory pointers
56 With STM32 MDMA linked-list mode, a single request initiates the data array
57 (collection of nodes) to be transferred until the linked-list pointer for the
60 case, the linked-list loops on to create a circular MDMA transfer.
[all …]
/linux-6.14.4/drivers/cpufreq/
Dsa1110-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-sa1100/cpu-sa1110.c
8 * 7 - SDRAM auto-power-up failure (rev A0)
9 * 13 - Corruption of internal register reads/writes following
25 #include <asm/mach-types.h>
51 .name = "TC59SM716-CL2",
60 .name = "TC59SM716-CL3",
77 }, { /* Samsung K4S281632B-1H */
78 .name = "K4S281632B-1H",
103 }, { /* Micron MT48LC8M16A2TG-75 */
[all …]
/linux-6.14.4/Documentation/RCU/
Dstallwarn.rst1 .. SPDX-License-Identifier: GPL-2.0
9 options that can be used to fine-tune the detector's operation. Finally,
20 - A CPU looping in an RCU read-side critical section.
22 - A CPU looping with interrupts disabled.
24 - A CPU looping with preemption disabled.
26 - A CPU looping with bottom halves disabled.
28 - For !CONFIG_PREEMPTION kernels, a CPU looping anywhere in the
33 - Booting Linux using a console connection that is too slow to
34 keep up with the boot-time console-message rate. For example,
36 with boot-time message rates, and will frequently result in
[all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/snowridgex/
Duncore-interconnect.json111 "BriefDescription": "FAF allocation -- sent to ADQ",
148 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
158 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
168 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
178 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
188 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
198 … "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
208 … "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
218 "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch",
228 "BriefDescription": "Misc Events - Set 1 : Lost Forward",
[all …]
/linux-6.14.4/drivers/media/rc/img-ir/
Dimg-ir-sharp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2012-2014 Imagination Technologies Ltd.
8 #include "img-ir-hw.h"
17 return -EINVAL; in img_ir_sharp_scancode()
26 return -EINVAL; in img_ir_sharp_scancode()
28 /* probably the second half of the message */ in img_ir_sharp_scancode()
29 return -EINVAL; in img_ir_sharp_scancode()
31 request->protocol = RC_PROTO_SHARP; in img_ir_sharp_scancode()
32 request->scancode = addr << 8 | cmd; in img_ir_sharp_scancode()
43 addr = (in->data >> 8) & 0x1f; in img_ir_sharp_filter()
[all …]
/linux-6.14.4/kernel/rcu/
DKconfig.debug1 # SPDX-License-Identifier: GPL-2.0-only
3 # RCU-related debugging configuration options
19 false-positive splats, we keep it default disabled but once all
63 Note that PREEMPT_COUNT must be enabled if the preempt-disabled
64 and bh-disabled checks are to take effect, and that PREEMPT_RCU
65 must be enabled for the RCU-nesting checks to take effect.
78 log of failure/close-call rcutorture reader segments with the
88 tristate "Scalability tests for read-side synchronization (RCU and others)"
94 useful comparing RCU with various read-side synchronization mechanisms.
108 If a given RCU grace period extends more than the specified
[all …]
Dtree.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Read-Copy Update mechanism for mutual exclusion (tree-based version)
4 * Internal non-public definitions.
39 * Definition for node within the RCU grace-period-detection hierarchy.
45 unsigned long gp_seq; /* Track rsp->gp_seq. */
49 /* order for current grace period to proceed.*/
56 /* Per-GP initial value for qsmask. */
57 /* Initialized from ->qsmaskinitnext at the */
58 /* beginning of each grace period. */
64 /* Per-GP initial values for expmask. */
[all …]
/linux-6.14.4/drivers/watchdog/
Dpic32-wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <asm/mach-pic32/pic32.h>
46 return !!(readl(wdt->regs + WDTCON_REG) & WDTCON_WIN_EN); in pic32_wdt_is_win_enabled()
51 u32 v = readl(wdt->regs + WDTCON_REG); in pic32_wdt_get_post_scaler()
58 u32 v = readl(wdt->regs + WDTCON_REG); in pic32_wdt_get_clk_id()
65 u32 v = readl(wdt->rst_base); in pic32_wdt_bootstatus()
67 writel(RESETCON_WDT_TIMEOUT, PIC32_CLR(wdt->rst_base)); in pic32_wdt_bootstatus()
75 u32 period, ps, terminal; in pic32_wdt_get_timeout_secs() local
77 rate = clk_get_rate(wdt->clk); in pic32_wdt_get_timeout_secs()
82 /* default, prescaler of 32 (i.e. div-by-32) is implicit. */ in pic32_wdt_get_timeout_secs()
[all …]
Drzn1_wdt.c1 // SPDX-License-Identifier: GPL-2.0
4 * This is a 12-bit timer driver from a (62.5/16384) MHz clock. It can't even
56 writel(0, wdt->base + RZN1_WDT_RETRIGGER); in rzn1_wdt_ping()
69 * timeout once started. Also note that the WDT clock is half the bus in rzn1_wdt_start()
76 val |= compute_reload_value(w->max_hw_heartbeat_ms, wdt->clk_rate_khz); in rzn1_wdt_start()
77 writel(val, wdt->base + RZN1_WDT_RETRIGGER); in rzn1_wdt_start()
103 struct device *dev = &pdev->dev; in rzn1_wdt_probe()
105 struct device_node *np = dev->of_node; in rzn1_wdt_probe()
113 return -ENOMEM; in rzn1_wdt_probe()
115 wdt->base = devm_platform_ioremap_resource(pdev, 0); in rzn1_wdt_probe()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/memory-controllers/
Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <[email protected]>
11 - Roger Quadros <[email protected]>
24 gpmc,sync-clk-ps:
25 description: Minimum clock period for synchronous mode
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
[all …]
/linux-6.14.4/Documentation/scheduler/
Dsched-bwc.rst7 The SCHED_RT case is covered in Documentation/scheduler/sched-rt-group.rst
12 The bandwidth allowed for a group is specified using a quota and period. Within
13 each given "period" (microseconds), a task group is allocated up to "quota"
14 microseconds of CPU time. That quota is assigned to per-cpu run queues in
18 period when the quota is replenished.
21 cfs_quota units at each period boundary. As threads consume this bandwidth it
22 is transferred to cpu-local "silos" on a demand basis. The amount transferred
26 -------------
30 Traditional (UP-EDF) bandwidth control is something like:
66 https://lore.kernel.org/lkml/5371BD36-55AE-4F71-B9D7-[email protected]/
[all …]
/linux-6.14.4/Documentation/filesystems/
Dqnx6.rst1 .. SPDX-License-Identifier: GPL-2.0
29 ------
39 ---------------
50 (or period) and building up a new (stable) filesystem structure under the
65 Unused block pointers are always set to ~0 - regardless of root node,
79 0x1000 is the size reserved for each superblock - regardless of the
83 ------
104 -----------
125 -------------
141 --------------
[all …]
/linux-6.14.4/Documentation/userspace-api/media/v4l/
Dfunc-read.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. _func-read:
13 v4l2-read - Read from a V4L2 device
18 .. code-block:: c
64 only the period of the vertical blanking interval is available for
69 period or the vertical blanking separating the top and bottom field
78 implies a reduction of the capture rate to one half or less of the
101 :c:func:`read()` was interrupted by a signal. On error, -1 is
107 Non-blocking I/O has been selected using O_NONBLOCK and no data was
/linux-6.14.4/sound/arm/
Daaci.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
82 #define SR_TXHE (1 << 3) /* tx fifo half empty */
83 #define SR_RXHF (1 << 2) /* rx fifo half full */
134 #define SLFR_RWIS (1 << 13) /* raw wake-up interrupt status */
210 unsigned int period; /* byte size of a "period" */ member
/linux-6.14.4/drivers/pwm/
Dpwm-sun4i.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 * - When outputing the source clock directly, the PWM logic will be bypassed
9 * and the currently running period is not guaranteed to be completed
47 #define PWM_PRD(prd) (((prd) - 1) << 16)
100 return readl(sun4ichip->base + offset); in sun4i_pwm_readl()
106 writel(val, sun4ichip->base + offset); in sun4i_pwm_writel()
118 clk_rate = clk_get_rate(sun4ichip->clk); in sun4i_pwm_get_state()
120 return -EINVAL; in sun4i_pwm_get_state()
129 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && in sun4i_pwm_get_state()
[all …]
/linux-6.14.4/drivers/rtc/
Drtc-sh.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH On-Chip RTC Support
5 * Copyright (C) 2006 - 2009 Paul Mundt
38 #define DRV_NAME "sh-rtc"
72 /* ALARM Bits - or with BCD encoded value */
75 /* Period Bits */
76 #define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */
77 #define PF_COUNT 0x200 /* Half periodic counter */
92 #define RCR2_ADJ 0x04 /* ADJustment (30-second) */
114 tmp = readb(rtc->regbase + RCR1); in __sh_rtc_interrupt()
[all …]

12345678910>>...13