| /linux-6.14.4/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-ipq806x.c | 2 * Qualcomm Atheros IPQ806x GMAC glue layer
115 static int get_clk_div_sgmii(struct ipq806x_gmac *gmac, unsigned int speed) in get_clk_div_sgmii() argument
117 struct device *dev = &gmac->pdev->dev; in get_clk_div_sgmii()
141 static int get_clk_div_rgmii(struct ipq806x_gmac *gmac, unsigned int speed) in get_clk_div_rgmii() argument
143 struct device *dev = &gmac->pdev->dev; in get_clk_div_rgmii()
167 static int ipq806x_gmac_set_speed(struct ipq806x_gmac *gmac, unsigned int speed) in ipq806x_gmac_set_speed() argument
172 switch (gmac->phy_mode) { in ipq806x_gmac_set_speed()
177 div = get_clk_div_rgmii(gmac, speed); in ipq806x_gmac_set_speed()
178 clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) | in ipq806x_gmac_set_speed()
179 NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id); in ipq806x_gmac_set_speed()
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| D | dwmac-sunxi.c | 32 struct sunxi_priv_data *gmac = priv; in sun7i_gmac_init() local
35 if (gmac->regulator) { in sun7i_gmac_init()
36 ret = regulator_enable(gmac->regulator); in sun7i_gmac_init()
41 /* Set GMAC interface port mode in sun7i_gmac_init()
43 * The GMAC TX clock lines are configured by setting the clock in sun7i_gmac_init()
47 if (phy_interface_mode_is_rgmii(gmac->interface)) { in sun7i_gmac_init()
48 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE); in sun7i_gmac_init()
49 clk_prepare_enable(gmac->tx_clk); in sun7i_gmac_init()
50 gmac->clk_enabled = 1; in sun7i_gmac_init()
52 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_MII_RATE); in sun7i_gmac_init()
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| D | dwmac-s32.c | 3 * NXP S32G/R GMAC glue layer
41 static int s32_gmac_write_phy_intf_select(struct s32_priv_data *gmac) in s32_gmac_write_phy_intf_select() argument
43 writel(PHY_INTF_SEL_RGMII, gmac->ctrl_sts); in s32_gmac_write_phy_intf_select()
45 dev_dbg(gmac->dev, "PHY mode set to %s\n", phy_modes(*gmac->intf_mode)); in s32_gmac_write_phy_intf_select()
52 struct s32_priv_data *gmac = priv; in s32_gmac_init() local
56 ret = clk_prepare_enable(gmac->tx_clk); in s32_gmac_init()
61 ret = clk_set_rate(gmac->tx_clk, GMAC_INTF_RATE_125M); in s32_gmac_init()
68 ret = clk_prepare_enable(gmac->rx_clk); in s32_gmac_init()
73 ret = clk_set_rate(gmac->rx_clk, GMAC_INTF_RATE_125M); in s32_gmac_init()
80 ret = s32_gmac_write_phy_intf_select(gmac); in s32_gmac_init()
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| D | dwmac-anarion.c | 27 static uint32_t gmac_read_reg(struct anarion_gmac *gmac, uint8_t reg) in gmac_read_reg() argument
29 return readl(gmac->ctl_block + reg); in gmac_read_reg()
32 static void gmac_write_reg(struct anarion_gmac *gmac, uint8_t reg, uint32_t val) in gmac_write_reg() argument
34 writel(val, gmac->ctl_block + reg); in gmac_write_reg()
40 struct anarion_gmac *gmac = priv; in anarion_gmac_init() local
43 gmac_write_reg(gmac, GMAC_RESET_CONTROL_REG, 1); in anarion_gmac_init()
45 sw_config = gmac_read_reg(gmac, GMAC_SW_CONFIG_REG); in anarion_gmac_init()
47 sw_config |= (gmac->phy_intf_sel & GMAC_CONFIG_INTF_SEL_MASK); in anarion_gmac_init()
48 gmac_write_reg(gmac, GMAC_SW_CONFIG_REG, sw_config); in anarion_gmac_init()
50 gmac_write_reg(gmac, GMAC_RESET_CONTROL_REG, 0); in anarion_gmac_init()
[all …]
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| D | dwmac-sun8i.c | 38 * @syscon_field reg_field for the syscon's gmac register
588 struct sunxi_priv_data *gmac = priv; in sun8i_dwmac_init() local
591 if (gmac->regulator) { in sun8i_dwmac_init()
592 ret = regulator_enable(gmac->regulator); in sun8i_dwmac_init()
599 if (gmac->use_internal_phy) { in sun8i_dwmac_init()
608 if (gmac->regulator) in sun8i_dwmac_init()
609 regulator_disable(gmac->regulator); in sun8i_dwmac_init()
776 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; in get_ephy_nodes() local
797 gmac->ephy_clk = of_clk_get(iphynode, 0); in get_ephy_nodes()
798 if (IS_ERR(gmac->ephy_clk)) in get_ephy_nodes()
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| D | Kconfig | 61 tristate "Adaptrum Anarion GMAC support"
65 Support for Adaptrum Anarion GMAC Ethernet controller.
106 tristate "MediaTek MT27xx GMAC support"
109 Support for MediaTek GMAC Ethernet controller.
158 tristate "NXP S32G/S32R GMAC support"
166 SOCs GMAC ethernet controller, ie. S32G2xx, S32G3xx and
197 tristate "STi GMAC support"
206 SOCs GMAC ethernet controller.
218 SOCs GMAC ethernet controller.
221 tristate "Allwinner GMAC support"
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| D | hwif.c | 64 /* GMAC older than 3.50 has no extended descriptors */ in stmmac_dwmac1_quirks()
108 bool gmac; member
128 .gmac = false,
147 .gmac = true,
166 .gmac = false,
187 .gmac = false,
209 .gmac = false,
231 .gmac = false,
253 .gmac = false,
276 .gmac = false,
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| /linux-6.14.4/Documentation/devicetree/bindings/net/ |
| D | rockchip-dwmac.yaml | 7 title: Rockchip 10/100/1000 Ethernet driver(GMAC)
18 - rockchip,px30-gmac
19 - rockchip,rk3128-gmac
20 - rockchip,rk3228-gmac
21 - rockchip,rk3288-gmac
22 - rockchip,rk3308-gmac
23 - rockchip,rk3328-gmac
24 - rockchip,rk3366-gmac
25 - rockchip,rk3368-gmac
26 - rockchip,rk3399-gmac
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| D | thead,th1520-gmac.yaml | 4 $id: http://devicetree.org/schemas/net/thead,th1520-gmac.yaml#
7 title: T-HEAD TH1520 GMAC Ethernet controller
13 The TH1520 GMAC is described in the TH1520 Peripheral Interface User Manual
26 The GMAC Registers consists of two parts
29 - AHB registers are use to configure GMAC core (DesignWare Core part).
30 GMAC core register consists of DMA registers and GMAC registers.
37 - thead,th1520-gmac
48 - thead,th1520-gmac
53 - description: DesignWare GMAC IP core registers
54 - description: GMAC APB registers
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| D | renesas,rzn1-gmac.yaml | 4 $id: http://devicetree.org/schemas/net/renesas,rzn1-gmac.yaml#
7 title: Renesas GMAC
17 - renesas,r9a06g032-gmac
18 - renesas,rzn1-gmac
29 - renesas,r9a06g032-gmac
30 - const: renesas,rzn1-gmac
49 compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac";
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| D | hisilicon-hix5hd2-gmac.txt | 1 Hisilicon hix5hd2 gmac controller
5 * "hisilicon,hix5hd2-gmac"
6 * "hisilicon,hi3798cv200-gmac"
7 * "hisilicon,hi3516a-gmac"
9 * "hisilicon,hisi-gmac-v1"
10 * "hisilicon,hisi-gmac-v2"
43 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
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| D | allwinner,sun7i-a20-gmac.yaml | 4 $id: http://devicetree.org/schemas/net/allwinner,sun7i-a20-gmac.yaml#
7 title: Allwinner A20 GMAC
18 const: allwinner,sun7i-a20-gmac
31 - description: GMAC main clock
56 gmac: ethernet@1c50000 {
57 compatible = "allwinner,sun7i-a20-gmac";
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| D | snps,dwmac.yaml | 39 - st,spear600-gmac
52 - allwinner,sun7i-a20-gmac
55 - allwinner,sun8i-r40-gmac
75 - renesas,r9a06g032-gmac
76 - renesas,rzn1-gmac
77 - rockchip,px30-gmac
78 - rockchip,rk3128-gmac
79 - rockchip,rk3228-gmac
80 - rockchip,rk3288-gmac
81 - rockchip,rk3308-gmac
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| D | mediatek-dwmac.yaml | 21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
35 - mediatek,mt2712-gmac
39 - mediatek,mt8195-gmac
43 - mediatek,mt8188-gmac
44 - const: mediatek,mt8195-gmac
155 compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
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| D | loongson,ls1b-gmac.yaml | 4 $id: http://devicetree.org/schemas/net/loongson,ls1b-gmac.yaml#
17 - Dual 10/100/1000Mbps GMAC controllers
30 - loongson,ls1b-gmac
38 - loongson,ls1b-gmac
89 compatible = "loongson,ls1b-gmac", "snps,dwmac-3.50a";
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| D | nxp,s32-dwmac.yaml | 8 title: NXP S32G2xx/S32G3xx/S32R45 GMAC ethernet controller
32 - description: Main GMAC registers
33 - description: GMAC PHY mode control register
43 - description: Main GMAC clock
75 reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */
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| D | ipq806x-dwmac.txt | 8 - compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac"
20 gmac: ethernet@37000000 {
22 compatible = "qcom,ipq806x-gmac";
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| /linux-6.14.4/drivers/clk/sunxi/ |
| D | clk-a20-gmac.c | 29 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
34 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
35 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
39 * The external 125 MHz reference is optional, i.e. GMAC can use its
40 * internal TX clock just fine. The A31 GMAC clock module does not have
43 * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
44 * and its internal TX clock for GMII and RGMII modes. The GMAC driver should
47 * Only the GMAC should use this clock. Altering the clock so that it doesn't
48 * match the GMAC's operation parameters will result in the GMAC not being
49 * able to send traffic out. The GMAC driver should set the clock rate and
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| /linux-6.14.4/drivers/net/ethernet/cortina/ |
| D | gemini.h | 2 /* Register definitions for Gemini GMAC Ethernet device driver
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
91 /* GMAC 0/1 DMA/TOE register */
145 /* GMAC Hash/Rx/Tx AHB Weighting register */
148 /* TOE GMAC 0/1 register */
332 /* GMAC DMA Control Register
366 /* GMAC Tx Weighting Control Register 0
386 /* GMAC Tx Weighting Control Register 1
410 /* GMAC DMA Tx Description Word 0 Register
434 /* GMAC DMA Tx Description Word 1 Register
[all …]
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| /linux-6.14.4/drivers/net/ethernet/hisilicon/hns/ |
| D | hns_dsaf_mac.h | 221 u64 rx_bad_bytes; /* only for gmac */
228 u64 rx_minto64; /* only for gmac */
240 u64 rx_vlan_pkts; /* only for gmac */
241 u64 rx_data_err; /* only for gmac */
242 u64 rx_align_err; /* only for gmac */
243 u64 rx_long_err; /* only for gmac */
253 u64 rx_filter_pkts; /* only for gmac */
254 u64 rx_filter_bytes; /* only for gmac */
255 u64 rx_fifo_overrun_err;/* only for gmac */
256 u64 rx_len_err; /* only for gmac */
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| /linux-6.14.4/Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun7i-a20-gmac-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun7i-a20-gmac-clk.yaml#
7 title: Allwinner A20 GMAC TX Clock
18 const: allwinner,sun7i-a20-gmac-clk
45 compatible = "allwinner,sun7i-a20-gmac-clk";
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| /linux-6.14.4/drivers/pinctrl/sunxi/ |
| D | pinctrl-sun6i-a31.c | 24 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
32 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
40 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
48 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
56 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
64 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
72 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
80 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
88 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
95 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
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| D | pinctrl-sun8i-a83t.c | 185 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD3 */
190 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD2 */
195 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD1 */
200 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD0 */
205 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXCK */
210 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXDV */
215 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXERR */
220 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD3 */
225 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD2 */
230 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD1 */
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| /linux-6.14.4/arch/arm64/boot/dts/allwinner/ |
| D | sun50i-h5-nanopi-neo-plus2.dts | 40 reg_gmac_3v3: gmac-3v3 {
42 regulator-name = "gmac-3v3";
51 reg_gmac_2v5: gmac-2v5 {
52 /* 2V5 supply for GMAC PHY IO */
54 regulator-name = "gmac-2v5";
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| /linux-6.14.4/arch/arm64/boot/dts/rockchip/ |
| D | rk3399-ficus.dts | 17 ethernet0 = &gmac;
24 clkin_gmac: external-gmac-clock {
79 &gmac {
100 gmac {
|