| /linux-6.14.4/Documentation/ABI/testing/ |
| D | sysfs-platform-intel-pmc | 6 The file exposes "Extended Test Mode Register 3" global
7 reset bits. The bits are used during an Intel platform
8 manufacturing process to indicate that consequent reset
9 of the platform is a "global reset". This type of reset
13 Display global reset setting bits for PMC.
15 * bit 31 - global reset is locked
16 * bit 20 - global reset is set
19 a platform "global reset" upon consequent platform reset,
21 The "global reset bit" should be locked on a production
22 system and the file is in read-only mode.
|
| /linux-6.14.4/Documentation/devicetree/bindings/reset/ |
| D | qcom,pdc-global.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/qcom,pdc-global.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PDC Global
10 - Sibi Sankar <[email protected]>
13 The bindings describes the reset-controller found on PDC-Global (Power Domain
19 - description: on SC7180 SoCs the following compatibles must be specified
21 - const: qcom,sc7180-pdc-global
22 - const: qcom,sdm845-pdc-global
[all …]
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| D | intel,rcu-gw.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: System Reset Controller on Intel Gateway SoCs
10 - Dilip Kota <[email protected]>
15 - intel,rcu-lgm
16 - intel,rcu-xrx200
19 description: Reset controller registers.
22 intel,global-reset:
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/soc/fsl/ |
| D | guts.txt | 1 * Global Utilities Block
3 The global utilities block controls power management, I/O device
4 enabling, power-on-reset configuration monitoring, general-purpose
10 - compatible : Should define the compatible device type for
11 global-utilities.
13 "fsl,qoriq-device-config-1.0"
14 "fsl,qoriq-device-config-2.0"
15 "fsl,<chip>-device-config"
16 "fsl,<chip>-guts"
17 - reg : Offset and length of the register set for the device.
[all …]
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| /linux-6.14.4/drivers/gpu/drm/i915/gt/ |
| D | selftest_hangcheck.c | 1 // SPDX-License-Identifier: MIT
47 h->gt = gt; in hang_init()
49 h->ctx = kernel_context(gt->i915, NULL); in hang_init()
50 if (IS_ERR(h->ctx)) in hang_init()
51 return PTR_ERR(h->ctx); in hang_init()
53 GEM_BUG_ON(i915_gem_context_is_bannable(h->ctx)); in hang_init()
55 h->hws = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in hang_init()
56 if (IS_ERR(h->hws)) { in hang_init()
57 err = PTR_ERR(h->hws); in hang_init()
61 h->obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in hang_init()
[all …]
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| D | intel_reset_types.h | 1 /* SPDX-License-Identifier: MIT */
15 * flags: Control various stages of the GPU reset
17 * #I915_RESET_BACKOFF - When we start a global reset, we need to
19 * any global resources that may be clobber by the reset (such as
22 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
23 * acquire the struct_mutex to reset an engine, we need an explicit
24 * flag to prevent two concurrent reset attempts in the same engine.
28 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
31 * aborted (with -EIO reported to userspace) if set.
33 * #I915_WEDGED_ON_INIT - If we fail to initialize the GPU we can no
[all …]
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| /linux-6.14.4/drivers/net/ethernet/aquantia/atlantic/hw_atl/ |
| D | hw_atl_llh.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
19 /* set temperature sense reset */
58 /* global */
60 /* set global microprocessor semaphore */
64 /* get global microprocessor semaphore */
67 /* set global register reset disable */
70 /* set soft reset */
73 /* get soft reset */
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/phy/ |
| D | st,stih407-usb2-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/st,stih407-usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <[email protected]>
19 const: st,stih407-usb2-phy
23 $ref: /schemas/types.yaml#/definitions/phandle-array
25 - items:
26 - description: phandle to syscfg
27 - description: phyparam register offset
[all …]
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| /linux-6.14.4/drivers/phy/st/ |
| D | phy-stih407-usb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/reset.h>
44 reset_control_deassert(phy_dev->rstc); in stih407_usb2_pico_ctrl()
46 return regmap_update_bits(phy_dev->regmap, phy_dev->ctrl, in stih407_usb2_pico_ctrl()
58 ret = regmap_update_bits(phy_dev->regmap, in stih407_usb2_init_port()
59 phy_dev->param, in stih407_usb2_init_port()
65 return reset_control_deassert(phy_dev->rstport); in stih407_usb2_init_port()
73 * Only port reset is asserted, phy global reset is kept untouched in stih407_usb2_exit_port()
74 * as other ports may still be active. When all ports are in reset in stih407_usb2_exit_port()
77 * reset (like here) or global reset should be equivalent. in stih407_usb2_exit_port()
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/clock/ |
| D | qcom,gcc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Common Properties
10 - Stephen Boyd <[email protected]>
11 - Taniya Das <[email protected]>
14 Common bindings for Qualcomm global clock control module providing the
18 '#clock-cells':
21 '#reset-cells':
24 '#power-domain-cells':
[all …]
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| D | qcom,mmcc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Multimedia Clock & Reset Controller
10 - Jeffrey Hugo <[email protected]>
11 - Taniya Das <[email protected]>
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8226
23 - qcom,mmcc-msm8660
[all …]
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| D | qcom,gcc-msm8916.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8916.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on MSM8916 and MSM8939
10 - Stephen Boyd <[email protected]>
11 - Taniya Das <[email protected]>
14 Qualcomm global clock control module provides the clocks, resets and power
18 include/dt-bindings/clock/qcom,gcc-msm8916.h
19 include/dt-bindings/clock/qcom,gcc-msm8939.h
[all …]
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| D | qcom,gcc-msm8660.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8660.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on MSM8660
10 - Stephen Boyd <[email protected]>
11 - Taniya Das <[email protected]>
14 Qualcomm global clock control module provides the clocks and resets on
18 include/dt-bindings/clock/qcom,gcc-msm8660.h
19 include/dt-bindings/reset/qcom,gcc-msm8660.h
[all …]
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| D | qcom,gcc-ipq6018.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-ipq6018.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ6018
10 - Stephen Boyd <[email protected]>
11 - Taniya Das <[email protected]>
12 - Robert Marko <[email protected]>
15 Qualcomm global clock control module provides the clocks, resets and power
19 include/dt-bindings/clock/qcom,gcc-ipq6018.h
[all …]
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| D | qcom,gcc-msm8974.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8974.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on MSM8974 (including Pro) and MSM8226
11 - Stephen Boyd <[email protected]>
12 - Taniya Das <[email protected]>
15 Qualcomm global clock control module provides the clocks, resets and power
19 include/dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
20 include/dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
[all …]
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| D | qcom,ipq9574-gcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ9574
10 - Bjorn Andersson <[email protected]>
11 - Anusha Rao <[email protected]>
14 Qualcomm global clock control module provides the clocks, resets and power
18 include/dt-bindings/clock/qcom,ipq9574-gcc.h
19 include/dt-bindings/reset/qcom,ipq9574-gcc.h
[all …]
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| D | qcom,ipq5018-gcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ5018
10 - Sricharan Ramabadhran <[email protected]>
13 Qualcomm global clock control module provides the clocks, resets and power
17 include/dt-bindings/clock/qcom,ipq5018-gcc.h
18 include/dt-bindings/reset/qcom,ipq5018-gcc.h
22 const: qcom,gcc-ipq5018
[all …]
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| D | qcom,gcc-mdm9607.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9607.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller
10 - Stephen Boyd <[email protected]>
11 - Taniya Das <[email protected]>
14 Qualcomm global clock control module provides the clocks, resets and power
18 include/dt-bindings/clock/qcom,gcc-mdm9607.h
21 - $ref: qcom,gcc.yaml#
[all …]
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| D | qcom,gcc-mdm9615.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9615.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller
10 - Stephen Boyd <[email protected]>
11 - Taniya Das <[email protected]>
14 Qualcomm global clock control module provides the clocks, resets and power
18 include/dt-bindings/clock/qcom,gcc-mdm9615.h
21 - $ref: qcom,gcc.yaml#
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,imx93-src.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx93-src.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX93 System Reset Controller
10 - Peng Fan <[email protected]>
13 The System Reset Controller (SRC) is responsible for the generation of
14 all the system reset signals and boot argument latching.
17 - Deals with all global system reset sources from other modules,
18 and generates global system reset.
[all …]
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| /linux-6.14.4/arch/x86/include/uapi/asm/ |
| D | debugreg.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
7 debug registers. Registers 0-3 contain the addresses we wish to trap on */
28 #define DR_STEP (0x4000) /* single-step */
33 bits - each field corresponds to one of the four debug registers,
51 that the processor will reset the bit after a task switch and the other
52 is global meaning that we have to explicitly reset the bit. With linux,
57 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit */
59 #define DR_GLOBAL_ENABLE (0x2) /* Global enable for reg 0 */
63 #define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
76 #define DR_GLOBAL_SLOWDOWN (0x200) /* Global slow the pipeline */
|
| /linux-6.14.4/drivers/clk/qcom/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
41 tristate "X1E80100 Global Clock Controller"
45 Support for the global clock controller on Qualcomm Technologies, Inc
164 tristate "APQ8084 Global Clock Controller"
168 Support for the global clock controller on apq8084 devices.
212 tristate "IPQ4019 Global Clock Controller"
214 Support for the global clock controller on ipq4019 devices.
219 tristate "IPQ5018 Global Clock Controller"
222 Support for global clock controller on ipq5018 devices.
227 tristate "IPQ5332 Global Clock Controller"
[all …]
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| /linux-6.14.4/drivers/gpu/drm/i915/gt/uc/ |
| D | selftest_guc_hangcheck.c | 1 // SPDX-License-Identifier: MIT
38 struct i915_gpu_error *global = >->i915->gpu_error; in intel_hang_guc() local
47 ctx = kernel_context(gt->i915, NULL); in intel_hang_guc()
53 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in intel_hang_guc()
62 reset_count = i915_reset_count(global); in intel_hang_guc()
64 old_beat = engine->props.heartbeat_interval_ms; in intel_hang_guc()
71 ret = igt_spinner_init(&spin, engine->gt); in intel_hang_guc()
95 gt_err(gt, "Failed to reset GuC: %pe\n", ERR_PTR(ret)); in intel_hang_guc()
99 guc_status = intel_uncore_read(gt->uncore, GUC_STATUS); in intel_hang_guc()
102 gt_err(gt, "Failed to reset GuC: status = 0x%08X\n", guc_status); in intel_hang_guc()
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <[email protected]>
15 - enum:
16 - qcom,sa8775p-pcie-ep
17 - qcom,sdx55-pcie-ep
18 - qcom,sm8450-pcie-ep
19 - items:
[all …]
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| /linux-6.14.4/drivers/net/phy/ |
| D | spi_ks8995.c | 1 // SPDX-License-Identifier: GPL-2.0
26 /* ------------------------------------------------------------------------ */
31 #define KS8995_REG_GC0 0x02 /* Global Control 0 */
32 #define KS8995_REG_GC1 0x03 /* Global Control 1 */
33 #define KS8995_REG_GC2 0x04 /* Global Control 2 */
34 #define KS8995_REG_GC3 0x05 /* Global Control 3 */
35 #define KS8995_REG_GC4 0x06 /* Global Control 4 */
36 #define KS8995_REG_GC5 0x07 /* Global Control 5 */
37 #define KS8995_REG_GC6 0x08 /* Global Control 6 */
38 #define KS8995_REG_GC7 0x09 /* Global Control 7 */
[all …]
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