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/linux-6.14.4/Documentation/devicetree/bindings/firmware/
Dqemu,fw-cfg-mmio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/firmware/qemu,fw-cfg-mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <[email protected]>
16 - A write-only, 16-bit wide selector (or control) register,
17 - a read-write, 64-bit wide data register.
23 The authoritative guest-side hardware interface documentation to the fw_cfg
29 const: qemu,fw-cfg-mmio
39 dma-coherent: true
[all …]
/linux-6.14.4/drivers/gpu/drm/i915/gvt/
Dfirmware.c2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
58 struct intel_gvt_device_info *info = &gvt->device_info; in expose_firmware_sysfs()
59 struct drm_i915_private *i915 = gvt->gt->i915; in expose_firmware_sysfs()
60 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); in expose_firmware_sysfs()
67 size = offsetof(struct gvt_firmware_header, data) + info->mmio_size + info->cfg_space_size; in expose_firmware_sysfs()
70 return -ENOMEM; in expose_firmware_sysfs()
74 h->magic = VGT_MAGIC; in expose_firmware_sysfs()
75 h->version = FIRMWARE_VERSION; in expose_firmware_sysfs()
76 h->cfg_space_size = info->cfg_space_size; in expose_firmware_sysfs()
77 h->cfg_space_offset = offsetof(struct gvt_firmware_header, data); in expose_firmware_sysfs()
[all …]
/linux-6.14.4/arch/powerpc/kvm/
Dpowerpc.c1 // SPDX-License-Identifier: GPL-2.0-only
52 return !!(v->arch.pending_exceptions) || kvm_request_pending(v); in kvm_arch_vcpu_runnable()
96 vcpu->run->exit_reason = KVM_EXIT_INTR; in kvmppc_prepare_to_enter()
97 r = -EINTR; in kvmppc_prepare_to_enter()
101 vcpu->mode = IN_GUEST_MODE; in kvmppc_prepare_to_enter()
104 * Reading vcpu->requests must happen after setting vcpu->mode, in kvmppc_prepare_to_enter()
144 struct kvm_vcpu_arch_shared *shared = vcpu->arch.shared; in kvmppc_swab_shared()
147 shared->sprg0 = swab64(shared->sprg0); in kvmppc_swab_shared()
148 shared->sprg1 = swab64(shared->sprg1); in kvmppc_swab_shared()
149 shared->sprg2 = swab64(shared->sprg2); in kvmppc_swab_shared()
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/linux-6.14.4/sound/soc/sof/mediatek/mt8195/
Dmt8195.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
24 #include "../../sof-of-dev.h"
25 #include "../../sof-audio.h"
27 #include "../mtk-adsp-common.h"
29 #include "mt8195-clk.h"
44 struct adsp_priv *priv = sdev->pdata->hw_pdata; in mt8195_send_msg()
46 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, in mt8195_send_msg()
47 msg->msg_size); in mt8195_send_msg()
49 return mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_REQ, MTK_ADSP_IPC_OP_REQ); in mt8195_send_msg()
57 spin_lock_irqsave(&priv->sdev->ipc_lock, flags); in mt8195_dsp_handle_reply()
[all …]
/linux-6.14.4/sound/soc/sof/mediatek/mt8186/
Dmt8186.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
5 // Author: Allen-KH Cheng <allen-[email protected]>
24 #include "../../sof-of-dev.h"
25 #include "../../sof-audio.h"
27 #include "../mtk-adsp-common.h"
29 #include "mt8186-clk.h"
44 struct adsp_priv *priv = sdev->pdata->hw_pdata; in mt8186_send_msg()
46 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, in mt8186_send_msg()
47 msg->msg_size); in mt8186_send_msg()
49 return mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_REQ, MTK_ADSP_IPC_OP_REQ); in mt8186_send_msg()
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/linux-6.14.4/arch/arm64/boot/dts/ti/
Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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Dk3-am65-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "simple-bus";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 cpsw_mac_syscon: ethernet-mac-syscon@200 {
16 compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
21 compatible = "ti,am654-phy-gmii-sel";
23 #phy-cells = <1>;
29 compatible = "pinctrl-single";
[all …]
Dk3-am64-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
[all …]
Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
[all …]
Dk3-j721s2-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
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Dk3-j7200-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
[all …]
Dk3-j721e-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
[all …]
Dk3-j784s4-j742s2-main-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
12 #include "k3-serdes.h"
15 serdes_refclk: clock-serdes {
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
29 compatible = "mmio-sram";
[all …]
Dk3-j784s4-j742s2-mcu-wakeup-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
9 sms: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 bootph-all;
23 compatible = "ti,sci-pm-domain";
[all …]
Dk3-j721s2-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
9 sms: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
[all …]
Dk3-j7200-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
[all …]
/linux-6.14.4/drivers/remoteproc/
Dqcom_wcnss.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
155 static int wcnss_load(struct rproc *rproc, const struct firmware *fw) in wcnss_load() argument
157 struct qcom_wcnss *wcnss = rproc->priv; in wcnss_load()
160 ret = qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID, in wcnss_load()
161 wcnss->mem_region, wcnss->mem_phys, in wcnss_load()
162 wcnss->mem_size, &wcnss->mem_reloc); in wcnss_load()
166 qcom_pil_info_store("wcnss", wcnss->mem_phys, wcnss->mem_size); in wcnss_load()
176 val = readl(wcnss->spare_out); in wcnss_indicate_nv_download()
178 writel(val, wcnss->spare_out); in wcnss_indicate_nv_download()
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/linux-6.14.4/drivers/accel/ivpu/
Dvpu_boot_api.h1 /* SPDX-License-Identifier: MIT */
3 * Copyright (c) 2020-2024, Intel Corporation.
11 * fw_bin_header->api_version[VPU_BOOT_API_VER_ID] = (VPU_BOOT_API_VER_MAJOR << 16) |
68 * Size of primary preemption buffer, assuming a 2-job submission queue.
74 * Size of secondary preemption buffer, assuming a 2-job submission queue.
79 /* Space reserved for future preemption-related fields. */
81 /* FW image read only section start address, 4KB aligned */
83 /* FW image read only section size, 4KB aligned */
125 * a specific VPU FW binary may support only a subset of such output
168 u8 cfg; member
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/linux-6.14.4/drivers/net/wireless/ath/wcn36xx/
Dmain.c190 return NL80211_IFTYPE_STATION == vif->type ? in get_sta_index()
191 sta_priv->bss_sta_index : in get_sta_index()
192 sta_priv->sta_index; in get_sta_index()
200 if (wcn36xx_firmware_get_feat_caps(wcn->fw_feat_caps, i)) { in wcn36xx_feat_caps_info()
201 wcn36xx_dbg(WCN36XX_DBG_MAC, "FW Cap %s\n", in wcn36xx_feat_caps_info()
209 struct wcn36xx *wcn = hw->priv; in wcn36xx_start()
263 INIT_LIST_HEAD(&wcn->vif_list); in wcn36xx_start()
264 spin_lock_init(&wcn->dxe_lock); in wcn36xx_start()
265 spin_lock_init(&wcn->survey_lock); in wcn36xx_start()
283 struct wcn36xx *wcn = hw->priv; in wcn36xx_stop()
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/linux-6.14.4/arch/arm/boot/dts/ti/omap/
Dam4372.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/am4.h>
15 interrupt-parent = <&wakeupgen>;
16 #address-cells = <1>;
17 #size-cells = <1>;
41 #address-cells = <1>;
[all …]
/linux-6.14.4/drivers/firmware/
Dqemu_fw_cfg.c7 * sysfs (read-only, under "/sys/firmware/qemu_fw_cfg/...").
15 * [qemu_fw_cfg.]mmio=<size>@<base>[:<ctrl_off>:<data_off>[:<dma_off>]]
18 * <size> := size of ioport or mmio range
19 * <base> := physical base address of ioport or mmio range
27 * qemu_fw_cfg.mmio=16@0x9020000:8:0:16 (the default on arm)
46 /* fw_cfg revision attribute, in /sys/firmware/qemu_fw_cfg top-level dir. */
80 u32 ctrl = be32_to_cpu(READ_ONCE(d->control)); in fw_cfg_wait_for_control()
82 /* do not reorder the read to d->control */ in fw_cfg_wait_for_control()
99 ret = -ENOMEM; in fw_cfg_dma_transfer()
113 /* force memory to sync before notifying device via MMIO */ in fw_cfg_dma_transfer()
[all …]
/linux-6.14.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dgf100.c51 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_zbc_clear_color()
52 if (gr->zbc_color[zbc].format) { in gf100_gr_zbc_clear_color()
53 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); in gf100_gr_zbc_clear_color()
54 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); in gf100_gr_zbc_clear_color()
55 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); in gf100_gr_zbc_clear_color()
56 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); in gf100_gr_zbc_clear_color()
58 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); in gf100_gr_zbc_clear_color()
67 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; in gf100_gr_zbc_color_get()
68 int zbc = -ENOSPC, i; in gf100_gr_zbc_color_get()
70 for (i = ltc->zbc_color_min; i <= ltc->zbc_color_max; i++) { in gf100_gr_zbc_color_get()
[all …]
/linux-6.14.4/drivers/net/wireless/mediatek/mt76/
Dmt76_connac_mcu.c1 // SPDX-License-Identifier: ISC
108 struct mt76_dev *dev = phy->dev; in mt76_connac_mcu_set_channel_domain()
112 n_max_channels = phy->sband_2g.sband.n_channels + in mt76_connac_mcu_set_channel_domain()
113 phy->sband_5g.sband.n_channels + in mt76_connac_mcu_set_channel_domain()
114 phy->sband_6g.sband.n_channels; in mt76_connac_mcu_set_channel_domain()
119 return -ENOMEM; in mt76_connac_mcu_set_channel_domain()
123 for (i = 0; i < phy->sband_2g.sband.n_channels; i++) { in mt76_connac_mcu_set_channel_domain()
124 chan = &phy->sband_2g.sband.channels[i]; in mt76_connac_mcu_set_channel_domain()
125 if (chan->flags & IEEE80211_CHAN_DISABLED) in mt76_connac_mcu_set_channel_domain()
128 channel.hw_value = cpu_to_le16(chan->hw_value); in mt76_connac_mcu_set_channel_domain()
[all …]
/linux-6.14.4/drivers/ata/
Data_piix.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ata_piix.c - Intel PATA/SATA controllers
6 * Please ALWAYS copy linux-[email protected]
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
14 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
15 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
19 * as Documentation/driver-api/libata.rst
40 * PIIX4 errata #9 - Only on ultra obscure hw
41 * ICH3 errata #13 - Not observed to affect real hw
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/linux-6.14.4/drivers/pci/
Dquirks.c1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
5 * should be handled in arch-specific code.
22 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */
106 int ret = -ENOTTY; in pcie_failed_link_retrain()
109 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) in pcie_failed_link_retrain()
117 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); in pcie_failed_link_retrain()
175 if ((f->class == (u32) (dev->class >> f->class_shift) || in pci_do_fixups()
176 f->class == (u32) PCI_ANY_ID) && in pci_do_fixups()
177 (f->vendor == dev->vendor || in pci_do_fixups()
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